Intel PXA255 - Manual (Page 492)

14-4 Intel® PXA255 Processor Developer’s Manual
Inter-Integrated-Circuit Sound (I2S) Controller
2. Choose between Normal I 2 S or MSB-Justified modes of operation. This can be done by
programming bit 0 of Serial Audio Controller I 2 S/MSB-Justified Control Register (SACR1).
For further details, see Section 14.6.2 .
3. Optional: Programmed I/O may be used for priming the Transmit FIFO with a few samples
(ranging from 1 to 16). If the I2SLINK is enabled with an empty Transmit FIFO, a Transmit
Under-run error bit will be set in the Status register. For further details, see Section 14.6.3 .
This is hence an optional step, which prevents such an error. If Step 3 is not executed, then
Programmed I/O must clear the Transmit Under-run status bit by setting bit 5 of the Interrupt
Clear Register. For further details, see Section 14.6.5 .
4. The following control bits can be simultaneously programmed in the I2SC’s Serial Audio
Controller Global Control register (SACR0):
a. Enable I2SLINK by setting the ENB bit (bit-0) of SACR0.
b. Maintain BITCLK direction as programmed in Step1. Modifying BITCLK direction will
glitch the clock and affect I2SLINK activity.
c. Program transmit and receive threshold levels by programming the TFTH and RFTH bits
of SACR0[11:8] and SACR0(15:12), respectively. See Section 14.6.1.2 , regarding
permitted threshold levels.
Once the I2SLINK is enabled, frames filled with 0s will be transmitted if the Transmit FIFO is
still empty. This will set a Transmit Under-run status bit in SASR0. Step 3 can be executed to
avoid this error condition. Valid data is sent across the I2SLINK after filling the Transmit
FIFO with at least one sample. One sample consists of a 32-bit value with 16 bits each
dedicated to a left and a right value.
Enabling the I2SLINK will also cause zeros to be recorded by the I2SC until the CODEC
sends in valid data.
Enabling the I2SLINK also enables transmit and receive DMA Requests.
14.3.2 Disabling and Enabling Audio Replay
Audio transmission is enabled automatically when the I2SC is enabled. Transmission, or replay,
can be stopped by asserting the DRPL bit of the SACR1 Register. For more details, see
Section 14.6.2 .
Asserting the DRPL bit in SACR1 has the following effects:
1. All I2SLINK replay activity is disabled. The frame or data sample, in the midst of which the
replay is disabled, will have invalid data (some data bits will be over-written with zeros). To
avoid this, disable replay only after the transfer of valid data. In this case, frames with zeros
are transmitted.
2. Transmit FIFO pointers are reset to zero.
3. Transmit FIFO fill-level is reset to zero.
4. Zeros are transmitted across the I2SLINK.
5. Transmit DMA requests are disabled.
14.3.3 Disabling and Enabling Audio Record
Audio recording is enabled automatically when the I2SC is enabled. Recording can also be stopped
by asserting the DREC bit of the SACR1 Register. For more details, see
Section 14.6.2 .