Intel PXA255 - Manual (Page 385)

Intel® PXA255 Processor Developer’s Manual 10-27
UARTs
0x4020_001C X BTSPR Scratch Pad Register
0x4020_0020 X BTISR Infrared Selection register (read/write)
0x4020_0000 1 BTDLL Divisor Latch Low register (read/write)
0x4020_0004 1 BTDLH Divisor Latch High register (read/write)
Table 10-20. STUART Register Summary
Register Addresses
DLAB Bit
Value
Name Description
0x4070_0000 0 STRBR Receive Buffer register (read only)
0x4070_0000 0 STTHR Transmit Holding register (write only)
0x4070_0004 0 STIER IER (read/write)
0x4070_0008 X STIIR Interrupt ID register (read only)
0x4070_0008 X STFCR FCR (write only)
0x4070_000C X STLCR LCR (read/write)
0x4070_0010 X STMCR MCR (read/write)
0x4070_0014 X STLSR LSR (read only)
0x4070_0018 X STMSR reserved (no modem control pins)
0x4070_001C X STSPR Scratch Pad Register
0x4070_0020 X STISR Infrared Selection register (read/write)
0x4070_0000 1 STDLL Divisor Latch Low register (read/write)
0x4070_0004 1 STDLH Divisor Latch High register (read/write)
Table 10-19. BTUART Register Summary (Sheet 2 of 2)
Register Addresses
DLAB Bit
Value
Name Description