Intel PXA255 - Manual (Page 471)

Intel® PXA255 Processor Developer’s Manual 13-19
AC’97 Controller Unit
13.8.2 Interrupts
The following status bits interrupt the processor when the interrupts are enabled:
• Mic-in FIFO error: Mic-in Receive FIFO’s over-run or under-run error.
• Modem-in FIFO error: Modem Receive FIFO’s over-run or under-run error.
• PCM-in FIFO error: Audio Receive FIFO’s over-run or under-run error.
• Modem-out FIFO error: Modem Transmit FIFO’s over-run or under-run error.
• PCM-out FIFO error: Audio Transmit FIFO’s over-run or under-run error.
• Modem CODEC GPI status change interrupt: Interrupts the CPU if bit 0 of Slot 12 is set. This
indicates a change in one of the bits in the modem CODEC’s GPIO register.
• Primary CODEC resume interrupt: Sets a status register bit when the Primary CODEC
resumes from a lower power mode. Software writes a one to this bit to clear it.
• Secondary CODEC resume interrupt: Sets a status register bit when the Secondary CODEC
resumes from a lower power mode. Software writes a one to this bit to clear it.
• CODEC command done interrupt: Interrupts the CPU when a CODEC register’s command is
completed. Software writes a one to this bit to clear it.
• CODEC status done interrupt: Interrupts the CPU when a CODEC register’s status address
and data reception are completed. Software writes a one to this bit to clear it.
• Primary CODEC ready interrupt: Sets a status register bit when the Primary CODEC is ready.
The CODEC sets bit 0 of Slot 0 on the input frame to signal that it is ready. Software clears the
PRIRDY_IEN bit of the GCR to clear this interrupt.
• Secondary CODEC ready interrupt: Sets a status register bit when the Secondary CODEC is
ready. The CODEC sets bit 0 of Slot 0 on the input frame to signal that it is ready. Software
clears the SECRDY_IEN bit of the GCR to clear this interrupt.
13.8.3 Registers
The ACUNIT and CODEC registers are mapped in addresses ranging from 0x4050_0000 through
0x405F_FFFF. All ACUNIT registers are 32-bit addressable. Even though a CODEC has up to
sixty-four 16-bit registers that are 16-bit addressable, they are accessed via a 32-bit address map
and translated to 16-bits for the CODEC.
Programmed I/O and DMA bursts can access the following registers:
• Global registers: The ACUNIT has three global registers: Status, Control, and CODEC access
registers that are common to the audio and modem domains.
• Channel-specific audio ACUNIT registers refer to PCM-out, PCM-in, and mic-in channels.
• Channel-specific Modem ACUNIT registers refer to modem-out and modem-in channels.
• Audio CODEC registers
• Modem CODEC registers