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2 wake up triggered by the acunit, 6 acunit operation, 6 acunit operation -14 – Intel PXA255 User Manual

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13-14

Intel® PXA255 Processor Developer’s Manual

AC’97 Controller Unit

13.5.2.2

Wake Up Triggered by the ACUNIT

AC-link protocol provides for a cold AC’97 reset and a warm AC’97 reset. The current power-
down state ultimately dictates which AC’97 reset is used. Registers must stay in the same state

during all power-down modes unless a cold AC’97 reset is performed. In a cold AC’97 reset, the

AC’97 registers are initialized to their default values.

After a power down, the AC-link must wait for a minimum of four audio frame times after the

frame in which the power down occurred before it can be reactivated by reasserting the SYNC

signal. When AC-link powers up, it indicates readiness through the CODEC ready bit (input slot 0,

bit 15).

13.5.2.2.1

Cold AC’97 Reset

A cold reset is generated when the nACRESET pin is asserted by software setting the

COLD_RST bit of the GCR to zero. Asserting and deasserting nACRESET activates

SDATA_OUT and causes the CODEC to activate BITCLK. All AC’97 control registers are

initialized to their default power-on reset values. nACRESET is an asynchronous input to the

AC’97 CODEC.

13.5.2.2.2

Warm AC’97 Reset

A warm AC’97 reset reactivates the AC-link without altering the current AC’97 register

values. A warm reset is generated by software setting the WARM_RST bit of the GCR to one.

When BITCLK is absent, generation of a warm reset results in SYNC being driven high for a

minimum of one microsecond. The CODEC must not activate BITCLK until it samples SYNC
low again. This prevents a new audio frame from being falsely detected.

13.6

ACUNIT Operation

The ACUNIT can be accessed through the processor or the DMA controller. The processor uses

programmed I/O instructions to access the ACUNIT, and it can access four register types:

ACUNIT registers: Accessible at 32-bit boundaries. They are listed in

Section 13.8.3

.

CODEC registers: An audio or modem CODEC can contain up to sixty-four 16-bit registers. A

CODEC uses a 16-bit address boundary for registers. The ACUNIT supplies access to the

CODEC registers by mapping them to its 32-bit address domain boundary.

Section 13.8.3.17

describes the mapping from the 32-bit to 16-bit boundary. A write or read operation that

targets these registers is sent across the AC-link.

Modem CODEC GPIO register: If the ACUNIT is connected to a modem CODEC, the

CODEC GPIO register can also be accessed. The CODEC GPIO register uses access address

0x0054 in the CODEC domain. The GPIO write operation goes across the AC-link, but a read

does not. The GPIO register contents are continuously updated into a shadow register in the
ACUNIT when a frame is received from the CODEC. When the processor tries to read the

CODEC GPIO register, this shadow register is read instead.

ACUNIT FIFO data: The ACUNIT has two Transmit FIFOs for audio-out and modem-out and

three receive FIFOs for audio-in, modem-in, and mic-in. Data enters the transmit FIFOs by

writing to either the PCM Data Register (PCDR) or the Modem Data Register (MODR).