Intel PXA255 - Manual (Page 55)

Intel® PXA255 Processor Developer’s Manual 2-25
System Architecture
I2S 0x4040_0000
0x4040_0000 SACR0 Global Control Register
0x4040_0004 SACR1 Serial Audio I 2 S/MSB-Justified Control Register
0x4040_0008 — Reserved
0x4040_000C SASR0 Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register
0x4040_0010 — Reserved
0x4040_0014 SAIMR Serial Audio Interrupt Mask Register
0x4040_0018 SAICR Serial Audio Interrupt Clear Register
0x4040_001C
through
0x4040_005C
— Reserved
0x4040_0060 SADIV Audio Clock Divider Register.
0x4040_0064
through
0x4040_007C
— Reserved
0x4040_0080 SADR Serial Audio Data Register (TX and RX FIFO access Register).
AC97 0x4050_0000
0x4050_0000 POCR PCM Out Control Register
0x4050_0004 PICR PCM In Control Register
0x4050_0008 MCCR Mic In Control Register
0x4050_000C GCR Global Control Register
0x4050_0010 POSR PCM Out Status Register
0x4050_0014 PISR PCM In Status Register
0x4050_0018 MCSR Mic In Status Register
0x4050_001C GSR Global Status Register
0x4050_0020 CAR CODEC Access Register
0x4050_0024
through
0x4050_003C
— Reserved
0x4050_0040 PCDR PCM FIFO Data Register
0x4050_0044
through
0x4050_005C
— Reserved
0x4050_0060 MCDR Mic-in FIFO Data Register
0x4050_0064
through
0x4050_00FC
— Reserved
0x4050_0100 MOCR Modem Out Control Register
0x4050_0104 — Reserved
0x4050_0108 MICR Modem In Control Register
0x4050_010C — Reserved
0x4050_0110 MOSR Modem Out Status Register
Table 2-8. System Architecture Register Address Summary (Sheet 5 of 12)
Unit Address Register Symbol Register Description