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2 dma_irq signal, 3 dma channel priority scheme, Dma channel priority scheme -3 – Intel PXA255 User Manual

Page 153: Dreq timing requirements -3

2 dma_irq signal, 3 dma channel priority scheme, Dma channel priority scheme -3 | Dreq timing requirements -3 | Intel PXA255 User Manual | Page 153 / 600 2 dma_irq signal, 3 dma channel priority scheme, Dma channel priority scheme -3 | Dreq timing requirements -3 | Intel PXA255 User Manual | Page 153 / 600
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