2 os timer interrupt enable register (oier), Osmr[x] bit definitions -36, Oier bit definitions -36 – Intel PXA255 User Manual

Page 140: Table 4-41

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2 os timer interrupt enable register (oier), Osmr[x] bit definitions -36, Oier bit definitions -36 | Table 4-41 | Intel PXA255 User Manual | Page 140 / 600