Zilog Z80380 - Manual (Page 81)

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Z380 ™
U SER ' S M ANUAL Z ILOG
DC-8297-03
DIVUW
DIVIDE UNSIGNED (WORD)
DIVUW [HL,]src src = R, RX, IM, X
Operation: HL(15-0)
←
HL / src
HL(31-16)
←
remainder
The contents of the the HL register (dividend) are divided by the source operand (divisor)
and the quotient is stored in the lower word of the HL register; the remainder is stored in the
upper word of the HL register. The contents of the source are unaffected. Both operands are
treated as unsigned, binary integers. There are three possible outcomes of the DIVUW
instruction, depending on the division and the resulting quotient:
Case 1: If the quotient is less than 65536, then the quotient is left in the HL register, the
Overflow and Sign flags are cleared to 0, and the Zero flag is set according to the value of
the quotient.
Case 2: If the divisor is zero, the HL register is unchanged, the Zero and Overflow flags are
set to 1, and the Sign flag is cleared to 0.
Case 3: If the quotient is greater than or equal to 65536, the HL register is unchanged, the
Overflow flag is set to 1, and the Sign and Zero flags are cleared to 0.
Flags: S: Cleared
Z: Set if the quotient or divisor is zero; cleared otherwise
H: Unaffected
V: Set if the divisor is zero or if the computed quotient is greater than or equal to 65536;
cleared otherwise
N: Unaffected
C: Unaffected
Addressing Execute
Mode Syntax Instruction Format Time Note
R: DIVUW [HL,]R 11101101 11001011 101110rr 20
RX: DIVUW [HL,]RX 11101101 11001011 1011110y 20
IM: DIVUW [HL,]nn 11101101 11001011 10111111 -n(low)- -n(high) 20
X: DIVUW [HL,](XY+d) 11y11101 11001011 ——d— 10111010 22+r I
Field Encodings: rr: 00 for BC, 01 for DE, 11 for HL
y:
0 for IX, 1 for IY