Zilog Z80380 - Manual (Page 47)

5-13
Z380 ™
U SER ' S M ANUAL Z ILOG
DC-8297-03
5.5.9 External Input/Output Instruction
Group
This group of instructions (Table 5-14) are used for trans-
ferring a byte, a word, or string of bytes or words between
peripheral devices and the CPU registers or memory. Byte
I/O port addresses transfer bytes on D7-D0 only. These 8-
bit peripherals in a 16-bit data bus environment must be
connected to data line D7-D0. In an 8-bit data bus environ-
ment, word I/O instructions to external I/O peripherals
should not be used; however, on-chip peripherals which is
external to the CPU core and assigned as word I/O device
can still be accessed by word I/O instructions.
The instructions for transferring a single byte (IN, OUT) can
transfer data between any 8-bit CPU register or memory
address specified in the instruction and the peripheral port
specified by the contents of the C register. The IN instruc-
tion sets the CPU flags according to the input data;
however, special instructions restricted to using the CPU
accumulator and Direct Address mode and do not affect
the CPU flags. Another variant tests an input port specified
by the contents of the C register and sets the CPU flags
without modifying CPU registers or memory.
The instructions for transferring a single word (INW, OUTW)
can transfer data between the register pair and the periph-
eral port specified by the contents of the C register. For
Word I/O, the contents of B, D, or H appear on D7-D0 and
the contents of C, E, or L appear D15-D7. These instruc-
tions do not affect the CPU flags.
Also, there are I/O instructions available which allow to
specify 16-bit absolute I/O address (with DDIR decoder
directives, a 24-bit or 32-bit address is specified) is avail-
able. These instructions do not affect the CPU flags.
The remaining instructions in this group form a powerful
and complete complement of instructions for transferring
blocks of data between I/O ports and memory. The opera-
tion of these instructions is very similar to that of the block
move instructions described earlier, with the exception
that one operand is always an I/O port whose address
remains unchanged while the address of the other oper-
and (a memory location) is incremented or decremented.In
Word mode of transfer, the counter (i.e., BC register) holds
the number of transfers, rather than number of bytes to
transfer in memory-to-memory word block transfer. Both
byte and word forms of these instructions are available.
The automatically repeating forms of these instructions are
interruptible, like memory-to-memory transfer.
The I/O addresses output on the address bus is de-
pendant on the I/O instruction, as listed in Table 2-1.