Zilog Z80380 - Manual (Page 60)

5-26
Z380 ™
U SER ' S M ANUAL
DC-8297-03
Z ILOG
ADDW
ADD (WORD)
ADDW [HL,]src src = R, RX, IM, X
Operation: HL(15-0)
←
HL(15-0) + src(15-0)
The source operand is added to the HL register and the sum is stored in the HL register. The
contents of the source are unaffected. Two’s complement addition is performed.
Flags: S: Set if the result is negative; cleared otherwise
Z: Set if the result is zero; cleared otherwise
H: Set if there is a carry from bit 11 of the result; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the
result is of the opposite sign; cleared otherwise
N: Cleared
C: Set if there is a carry from the most significant bit of the result; cleared otherwise
Addressing Execute
Mode Syntax Instruction Format Time Note
R: ADDW [HL,]R 11101101 100001rr 2
RX: ADDW [HL,]RX 11y11101 10000111 2
IM: ADDW [HL,]nn 11101101 10000110 -n(low)- n(high)- 2
X: ADDW [HL,](XY+d) 11y11101 11000110 —d— 4+r I
Field Encodings: rr: 00 for BC, 01 for DE, 11 for HL
y:
0 for IX, 1 for IY