Zilog Z80380 - Manual (Page 173)

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Z380 ™
U SER ' S M ANUAL Z ILOG
DC-8297-03
RESC
RESET CONTROL BIT
RESC mode mode = LCK, LW
Operation: if (mode = LCK) then begin
SR(1)
←
0
end
else begin
SR(6)
←
0
end
When reseting Lock mode (LCK), the LCK bit (bit 1) in the Select Register (SR) is set to 0,
enabling external bus requests. Note that these requests cannot be granted until after the
instruction has been executed, and that one or more of the succeeding instructions may also
have been fetched for decoding before this instruction has been executed.
When reseting Long Word mode (LW), the LW bit (bit 6) in the SR is set to 0, selecting 16-
bit words. When using 16-bit words, all word load operations transfer 16 bits.
Flags: S: Unaffected
Z: Unaffected
H: Unaffected
V: Unaffected
N: Unaffected
C: Unaffected
Addressing Execute
Mode Syntax Instruction Format Time Note
RESC mode 11mm1101 11111111 4
Field Encodings: mm: 01 for LW, 10 for LCK