Zilog Z80380 - Manual (Page 222)

U SER ' S M ANUAL Z ILOG
7.1 INTRODUCTION
U SER ’s M ANUAL
C
HAPTER
7
R ESET
The Z380 CPU is placed in a dormant state when the
/RESET input is asserted. All its operations are terminated,
including any interrupt, bus request, or bus transaction
that may be in progress. On the Z380 MPU, the IOCLK
goes Low on the next BUSCLK rising edge and enters into
the BUSCLK divided-by-eight mode. The address and
data buses are tri-stated, and the bus control signals are
driven to their inactive states. The effect of /RESET on the
Z380 CPU and related internal I/O registers is depicted in
Table 7-1.
The /RESET input may be asynchronous to BUSCLK,
though it is sampled internally at BUSCLK’s falling edges.
For proper initialization of the Z380 CPU, V
DD
must be within
operating specifications and the CLK input must be stable
for more than five cycles with /RESET held Low.
The Z380 CPU proceeds to fetch the first instruction 3.5
BUSCLK cycles after /RESET is deasserted, provided
such deassertion meets the proper setup and hold times
with reference to the falling edge of BUSCLK. On the Z380
MPU implementation, with the proper setup and hold times
being met, IOCLK’s first rising edge is 11.5 BUSCLK
cycles after the /RESET deassertion, preceded by a mini-
mum of four BUSCLK cycles when IOCLK is at Low.
Note that if /BREQ is active when /RESET is deasserted, the
Z380 MPU would relinquish the bus instead of fetching its
first instruction. IOCLK synchronization would still take
place as described before.
Requirements to reset the device, and the initial state after
reset might be different depending on the particular imple-
mentation of the Z380 CPU on the individual Superintegra-
tion version of the device. For /RESET effects and require-
ments, refer to the individual product specification.