Zilog Z80380 - Manual (Page 7)

1-5
Z380 ™
U SER ' S M ANUAL Z ILOG
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are handled by a newly added interrupt handing mode,
“Assigned Vectored Mode,” which is a fixed vectored
interrupt mode similar in interrupt handling to the Z180’s
interrupts from on-chip peripherals. For handling interrupt
requests on the /INT0 line, there are four modes available:
■ 8080 compatible (Mode 0), in which the interrupting
device provides the first instruction of the interrupt
routine.
■ Dedicated interrupts (Mode 1), in which the CPU
jumps to a dedicated address when an interrupt
occurs.
■ Vectored interrupt mode (Mode 2), in which the
interrupting peripheral device provides a vector into a
table of jump address.
■ Enhanced vectored interrupt mode (Mode 3), wherein
the CPU expects 16-bit vector, instead of 8-bit interrupt
vectors in Mode 2.
The first three modes are compatible with Z80 interrupt
modes; the fourth mode provides more flexibility.
Traps are synchronous events that trigger a special CPU
response when an undefined instruction is executed. It
can be used to increase system reliability, or used as a
“software trap instruction.”
Hardware resets occur when the /RESET line is activated
and override all other conditions. A /RESET causes certain
CPU control registers to be initialized.
For details on this subject, refer to Chapter 6, “Interrupts
and Traps.”
1.3 BENEFITS OF THE ARCHITECTURE
The Z380 CPU architecture provides several significant
benefits, including increased program throughput achieved
by higher bus bandwidth (16-bit wide bus), reduction to
two clocks/basic machine cycle (vs four clocks/cycle on
the Z80 CPU), prefetch cue, access to the larger linear
addressing space, enhanced instructions/new address-
ing mode, data/address manipulation in 16/32 bits, and
faster context switching by utilizing multiple register banks.
1.3.1 High Throughput
Very high throughput rates can be achieved with the Z380
CPU, due to the basic machine cycle’s reduction to two
clocks/cycle from four clocks/cycle on the Z80 CPU, fine
tuned four staged pipeline with prefetch cue. This well
designed pipeline and prefetch cue are both totally trans-
parent to the user, thus maximizing the efficiency of the
pipeline all the time. The Z380 CPU implemented onto the
Z380 MPU is configured with a 16-bit wide data bus, which
doubles the bus bandwidth. These architectural features
result in two clocks/instructions execution minimum, three
clocks/instruction on average. The high clock rates (up to
40 MHz) achievable with this processor. Make the overall
performance of the Z380 CPU more than ten times that of
the Z80.
1.3.2 Linear Memory Address Space
Z380 CPU architecture has 4 Gbytes of linear memory
address space. The Z80 CPU architecture allows 64
Kbytes of memory addressing space. This was more than
sufficient when the Z80 CPU was first developed. But as
the technology improved over time, applications started to
demand more complicated processing, multitasking, faster
processing, etc., with the high level language needed to
develop software. As a result, 64 Kbytes of memory ad-
dressing space is not enough for some Z80 CPU based
applications. In order to handle more than 64 Kbytes of
memory, the Z80 CPU requires a Memory Banking scheme,
or MMU (Memory Management Unit), like the Z180 MPU or
Z280 MPU. These provide the overhead to access more
than 64 Kbytes of memory.
The Z380 CPU architecture allows access to a full 4 Gbytes
(2
32 ) of memory addressing space as well as 4 Gbytes of
I/O addressing area, without using a Memory Banking
scheme, or MMU.
1.3.3. Enhanced Instruction Set with 16-Bit
and 32-Bit Manipulation Capability
The Z380 CPU instruction set is 100% upward compatible
to the Z80 CPU instruction set; that is all the Z80 instruc-
tions have been preserved at the binary level. New instruc-
tions added to the Z380 CPU include:
■ Less restricted operand source/destination
combinations.
■ More flexible register exchange instructions.
■ Stack Pointer Relative addressing mode.