Zilog Z80380 User Manual

Page 39

5-5

Z380

™

SER

ANUAL

ILOG

DC-8297-03

5.3.8. Long Word Mode (LW)

This bit controls the Long Word/Word mode selection for
the Z380 CPU. This bit is set by the SETC LW instruction
and cleared by the RESC LW instruction. When this bit is
set, the Z380 CPU is in Long Word mode; when this bit is
cleared the Z380 CPU is in Word mode. Reset clears this
bit. Note that individual Word load and exchange instruc-
tions may be executed in either Word or Long Word mode
using the DDIR W and DDIR LW decoder directives.

5.3.9. Interrupt Enable Flag (IEF)

This bit is the master Interrupt Enable for the Z380 CPU.
This bit is set by the EI instruction and cleared by the DI
instruction, or on acknowledgment of an interrupt request.
When this bit is set, interrupts are enabled; when this bit is
cleared, interrupts are disabled. Reset clears this bit.

5.3.10. Interrupt Mode (IM)

This 2-bit field controls the interrupt mode for the /INT0
interrupt request. These bits are controlled by the IM
instructions (00 = IM 0, 01 = IM 1, 10 = IM 2, 11 = IM 3).
Reset clears both of these bits, selecting Interrupt Mode 0.

5.3.11. Lock (LCK)

This bit controls the Lock/Unlock status of the Z380 CPU.
This bit is set by the SETC LCK instruction and cleared by
the RESC LCK instruction. When this bit is set, no bus
requests will be accepted, providing exclusive access to
the bus by the Z380 CPU. When this bit is cleared, the Z380
CPU will grant bus requests in the normal fashion. Reset
clears this bit.

5.3.12. AF or AF’ Register Select (AF’)

This bit controls and reports whether AF or AF’ is the
currently active pair of registers. AF is selected when this
bit is cleared, and AF’ is selected when this bit is set. Reset
clears this bit, selecting AF.

5.4 INSTRUCTION EXECUTION AND EXCEPTIONS

Three types of exception conditions—interrupts, trap, and
Reset—can alter the normal flow of program execution.
Interrupts are asynchronous events generated by a device
external to the CPU; peripheral devices use interrupts to
request service from the CPU. Trap is a synchronous event
generated internally in the CPU by executing undefined
instructions. Reset is an asynchronous event generated by
outside circuits. It terminates all current activities and puts
the CPU into a known state. Interrupts and Traps are
discussed in detail in Chapter 6, and Reset is discussed in
detail in Chapter 7. This section examines the relationship
between instructions and the exception conditions.

5.4.1 Instruction Execution and Interrupts

When the CPU receives an interrupt request, and it is
enabled for interrupts of that class, the interrupt is normally
processed at the end of the current instruction. However,
the block transfer and search instructions are designed to
be interruptible so as to minimize the length of time it takes
the CPU to respond to an interrupt. If an interrupt request
is received during a block move, block search, or block
I/O instruction, the instruction is suspended after the
current iteration. The address of the instruction itself, rather
than the address of the following instruction, is saved on
the stack, so that the same instruction is executed again
when the interrupt handler executes an interrupt return

instruction. The contents of the repetition counter and the
registers that index into the block operands are such that,
after each iteration, when the instruction is reissued upon
returning from an interrupt, the effect is the same as if the
instruction were not interrupted. This assumes, of course,
that the interrupt handler preserves the registers.

5.4.2 Instruction Execution and Trap

The Z380 MPU generates a Trap when an undefined
opcode is encountered. The action of the CPU in response
to Trap is to jump to address 00000000H with the status
bit(s) set. This response is similar to the Z180 MPU’s action
on execution of an undefined instruction. The Trap is
enabled immediately after reset, and it is not maskable.
This feature can be used to increase software reliability or
to implement “extended” instructions. An undefined op-
code can be fetched from the instruction stream, or it can
be returned as a vector in an interrupt acknowledge
transaction in Interrupt mode 0.

Since it jumps to address 00000000H, it is necessary to
have a Trap handling routine at the beginning of the
program if processing is to proceed. Otherwise, it behaves
just like a reset for the CPU. For a detailed description, refer
to Chapter 6.