Zilog Z80380 - Manual (Page 152)

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Z380 ™
U SER ' S M ANUAL
DC-8297-03
Z ILOG
OTIMR
OUTPUT, INCREMENT MEMORY REPEAT
OTIMR
Operation: repeat until (B=0) begin
(C)
←
(HL)
C
←
C + 1
B
←
B – 1
HL
←
HL + 1
end
This instruction is used for block output of strings of data to on-chip peripherals. No external
I/O transaction will be generated as a result of this instruction, although the I/O address will
appear on the address bus and the write data will appear on the data bus while this internal
write is occurring. The peripheral address is placed on the low byte of the address bus and
zeros are placed on all other address lines. The byte of data from the memory location
addressed by the HL register is loaded to the on-chip I/O port addressed by the C register.
The C register, holding the port address, is incremented by one to select the next output port.
The B register, used as a counter, is then decremented by one. The HL register is then
incremented by one, thus moving the pointer to the next source for the output. If the result
of decrementing the B register is 0, the instruction is terminated, otherwise the output
sequence is repeated. Note that if the B register contains 0 at the start of the execution of
this instruction, 256 bytes are output.
This instruction can be interrupted after each execution of the basic operation. The Program
Counter value at the start of this instruction is saved before the interrupt request is accepted,
so that the instruction can be properly resumed.
Flags: S: Cleared
Z: Set
H: Cleared
P: Set
N: Set if the most significant bit of the byte transferred was a 1; cleared otherwsie
C: Cleared
Addressing Execute
Mode Syntax Instruction Format Time Note
OTIMR 11101101 10010011 2+r+o