Zilog Z80380 - Manual (Page 19)

2-4
Z380 ™
U SER ' S M ANUAL
DC-8297-03
Z ILOG
2.2.6 Stack Pointer (Continued)
Increment/decrement of the Stack Pointer is affected by
modes of operation (Native or Extended). In Native mode,
the stack operates in modulo 2
16 , and in Extended mode,
it operates in modulo 2 32 . For example, SP holds 0001FFFEH,
and does the Word size Pop operation. After the operation,
SP holds 00010000H in Native mode, and 00020000H in
Extended mode. In either case, SPz can be programmed
to set Stack frame. This is done by the Load- to-Stack
pointer instructions in Long Word mode.
2.3. CPU CONTROL REGISTER SPACE
The CPU control register space consists of the 32-bit
Select Register (SR). The SR may be accessed as a whole
or the upper three bytes of the SR may be accessed
individually as YSR, XSR, and DSR. In addition, these upper three bytes can be loaded with the same byte value.
The SR may also be PUSHed and POPed and is cleared to
zeros on Reset. For details on this register, refer to Chapter
5.3, “Select Register.”
2.4 MEMORY ADDRESS SPACE
The memory address space can be viewed as a string of
4 Gbytes numbered consecutively in ascending order.
The 8-bit byte is the basic addressable element in the Z380
MPU memory address space. However, there are other
addressable data elements: bits, 2-byte words, byte strings,
and 4-byte words.
The size of the data element being addressed depends on
the instruction being executed as well as the Word/Long
Word mode. A bit can be addressed by specifying a byte
and a bit within that byte. Bits are numbered from right to
left, with the least significant bit being 0, as illustrated in
Figure 2-2.
The address of a multiple-byte entity is the same as the
address of the byte with the lowest memory address in the
entity. Multiple-byte entities can be stored beginning with
either even or odd memory addresses. A word (either 2-
byte or 4-byte entity) is aligned if its address is even;
otherwise it is unaligned. Multiple bus transactions, which
may be required to access multiple-byte entities, can be
minimized if alignment is maintained.
The format of multiple-byte data types is also shown in
Figure 2-2. Note that when a word is stored in memory, the
least significant byte precedes the more significant byte of
the word, as in the Z80 CPU architecture. Also, the lower-
addressed byte is present on the upper byte of the external
data bus.