Zilog Z80380 - Manual (Page 32)

4-7
Z380 ™
U SER ' S M ANUAL Z ILOG
DC-8297-03
4.2.7 Stack Pointer Relative Mode (SR)
For Stack Pointer Relative addressing mode, the data
processed is at the location whose address is the contents
of the Stack Pointer, offset by an 8-bit displacement in the
instruction.
The Stack Pointer Relative address is computed by adding
the 8-bit two’s complement signed displacement speci-
fied in the instruction to the contents of the SP, also
specified by the instruction. Stack Pointer Relative ad-
dressing mode is used to specify data items to be found in
the stack, such as parameters passed to procedures.
Offset portion can be expanded to 16 or 24 bits by using
DDIR immediate instructions (DDIR IB for a 16-bit offset,
DDIR IW for a 24-bit offset).
Note that computation of the effective address is affected
by the operation mode (Native or Extended). In Native
mode, address computation is done in modulo 2
16 , mean-
ing computation is done in 16-bit and does not affect upper
half of the SP portion for calculation (wrap around within the
16-bit). In Extended mode, address computation is done
in modulo 2
32 .
Also, the size of the data transfer is affected by the LW
mode bit. In Word mode, transfer is done in 16 bits, and in
Long Word mode, transfer is done in 32 bits.
Instruction SP
OPERATION ADDRESS ——| MEMORY
DISPLACEMENT ——+ OPERAND
Example of SR mode:
1.
Load HL from location (SP – 4) in Native mode, Word mode
LD HL, (SP–4) ;Load into the HL from the
;contents of the memory location
;whose address is four less than
;the contents of SP.
;Assume it is in Native/Word mode.
HLz HL SPz SP
Before instruction execution 1234 5678 07FF 7F00
After instruction execution EFCD AB89 07FF 7F00
Memory location 07FF7EFC 89
07FF7EFD AB
Address calculation: In Native mode, FCH (–4 in Decimal)
encoding in the instruction is sign extended to a 16-bit
value before the address calculation. Calculation is done
in modulo 2
16 and does not take into account the Stack
Pointer’s extended portion.
7F00
+ FFFC
7EFC