Zilog Z80380 User Manual

Page 49

5-15

Z380

™

SER

ANUAL

ILOG

DC-8297-03

5.5.10 Internal I/O Instruction Group

This group (Table 5-15) of instructions is used to access
on-chip I/O addressing space on the Z380 CPU. This
group consists of instructions for transferring a byte from/
to Internal I/O locations and the CPU registers or memory,
or a blocks of bytes from the memory to the same size of
Internal I/O locations for initialization purposes. These
instructions are originally assigned as newly added I/O
instructions on the Z180 MPU to access Page 0 I/O
addressing space. There is 256 Internal I/O locations, and
all of them are byte-wide. When one of these I/O instruc-
tions is executed, the Z380 MPU outputs the register
address being accessed in a pseudo transaction of two
BUSCLK durations cycle, with the address signals A31-A8
at 0. In the pseudo transactions, all bus control signals are
at their inactive state.

The instructions for transferring a single byte (IN0, OUT0)
can transfer data between any 8-bit CPU register and the
Internal I/O address specified in the instruction. The IN0
instruction sets the CPU flags according to the input data;
however, special instructions which do not have a destina-

tion in the instruction with Direct Address (IN0 (n)), do not
affect the CPU register, but alters flags accordingly. An-
other variant, the TSTIO instruction, does a logical AND to
the instruction operand with the internal I/O location speci-
fied by the C register and changes the CPU flags without
modifying CPU registers or memory.

The remaining instructions in this group form a powerful
and complete complement of instructions for transferring
blocks of data from memory to Internal I/O locations. The
operation of these instructions is very similar to that of the
block move instructions described earlier, with the excep-
tion that one operand is always an Internal I/O location
whose address also increments or decrements by one
automatically, Also, the address of the other operand (a
memory location) is incremented or decremented. Since
Internal I/O space is byte-wide, only byte forms of these
instructions are available. Automatically repeating forms
of these instructions are interruptible, like memory-to-
memory transfer.

Table 5-15. Internal I/O Instruction Group

Instruction Name

Format

Input from Internal I/O Location

IN0 dst,(n)

dst=A, B, C, D, E, H or L

Input from Internal I/O Location(Nondestructive)

IN0 (n)

Test I/O

TSTIO n

Output to Internal I/O Location

OUT0 (n),src

src=A, B, C, D, E, H or L

Output to Internal I/O and Decrement

OTDM

Output to Internal I/O and Increment

OTIM

Output to Internal I/O, Decrement and Repeat

OTDMR

Output to Internal I/O, Increment and Repeat

OTIMR

Currently, the Z380 CPU core has the following registers as a part of the CPU core:

Register Name

Internal I/O address

Interrupt Enable Register

16H

Assigned Vector Base Register

17H

Trap Register

18H

Chip Version ID Register

0FFH

Chip Version ID register returns one byte data, which
indicates the version of the CPU, or the specific implemen-
tation of the Z380 CPU based Superintegration device.
Currently, the value 00H is assigned to the Z380 MPU, and
other values are reserved.

For the other three registers, refer to Chapter 6, “Interrupt
and Trap.”

Also, the Z380 MPU has registers to control chip selects,
refresh, waits, and I/O clock divide to Internal I/O address
00H to 10H. For these register, refer to Z380 MPU Product
specification.