Zilog Z80380 - Manual (Page 3)

U SER ' S M ANUAL Z ILOG
1.1 INTRODUCTION
U SER ’s M ANUAL
C
HAPTER
1
Z380 ™ A RCHITECTURAL O VERVIEW
The Z380 CPU incorporates advanced architectural fea-
tures that allow fast and efficient throughput and increased
memory addressing capabilities while maintaining Z80
®
CPU and Z180 ® MPU object-code compatibility. The Z380
CPU core provides a continuing growth path for present
Z80- or Z180
® -based designs and offers the following key
features:
■ Full Static CMOS Design with Low Power Standby
Mode Support
■ DC to 18 MHz Operating Frequency @ 5 Volts V
CC
■ DC to 10 MHz Operating Frequency @ 33 Volts V
CC
■ Enhanced Instruction Set that Maintains Object-Code
Compatibility with Z80 and Z180 Microprocessors
■ 16-Bit (64K) or 32-Bit (4G) Linear Address Space
■ 16-Bit Internal Data Bus
■ Two Clock Cycle Instruction Execution (Minimum)
■ Multiple On-Chip Register Files (Z380 MPU has Four
Banks)
■ BC/DE/HL/IX/IY Registers are Augmented by 16-Bit
Extended Registers (BCz/DEz/HLz/IXz/IYz), PC/SP/I
Registers are Augmented by Extended Registers (PCz/
SPz/Iz) for 32-Bit Addressing Capability.
■ Newly Added IX’ and IY’ Registers with Extended
Registers (IXz’/IYz’)
■ Enhanced Interrupt Capabilities, Including 16-Bit
Vector
■ Undefined Opcode Trap for Full Z380 CPU Instruction
Set
The Z380 CPU, an enhanced version of the Z80 CPU,
retains the Z80 CPU instruction set to maintain complete
binary-code compatiblity with present Z80 and Z180 codes.
The basic addressing modes of the Z80 microprocessor
have been augmented with Stack Pointer Relative loads
and stores, 16-bit and 24-bit Indexed offsets, and in-
creased Indirect register addressing flexibility, with all of
the addressing modes allowing access to the entire 32-bit
address space. Significant additions have been made to
the instruction set iincorporating16-bit arithmetic and logi-
cal operations, 16-bit I/O operations, multiply and divide,
a complete set of register-to-register loads and exchanges,
plus 32-bit load and exchange, and 32-bit arithmetic
operation for address calculation.
The basic register file of the Z80 microprocessor is ex-
panded to include alternate register versions of the IX and
IY registers. There are four sets of this basic Z80 micropro-
cessor register file present in the Z380 MPU, along with the
necessary resources to manage switching between the
different register sets. All of the register pairs and index
registers in the basic Z80 microprocessor register file are
expanded to 32 bits.
The Z380 CPU expands the basic 64 Kbyte Z80 and Z180
address space to a full 4 Gbyte (32-bit) address space.
This address space is linear and completely accessible to
the user program. The external I/O address space is
similarly expanded to a full 4 Gbyte (32-bit) range, and 16-
bit I/O, both simple and block move are included. A 256
byte-wide internal I/O space has been added. This space
will be used to access on-chip I/O resources on future
Superintegration implementation of this CPU core.
Figure 1-1 provides a detailed description of the basic
register architecture of the Z380 CPU with the size of the
register banks shown at four each, however, the Z380 CPU
architecture allows future expansion of up to 128 sets of
each.