Zilog Z80380 - Manual (Page 8)

1-6
Z380 ™
U SER ' S M ANUAL
DC-8297-03
Z ILOG
1.3.3. Enhanced Instruction Set with 16-Bit
and 32-Bit Manipulation Capability
(Continued)
■ DDIR (Decoder Directive Instructions) to enhance
addressing capability to cover 4 Gbytes of memory
space, as well as data manipulation capability.
■ Jump relative/Call relative instructions with 8-bit,
16-bit, or 24-bit displacement.
■ Full complements of 16-bit arithmetic instructions.
■ 32-bit manipulate instructions for address manipulation.
These new instructions help to compact the code, as well
as shorten the program’s overall execution speed.
For details on this subject, refer to Chapter 5, “Instruction
Set.”
1.3.4 Faster Context Switching
The Z380 CPU architecture allows multiple sets of register
banks for AF/AF’, BC/DE/HL, BC’/DE’/HL’, IX/IX’, IY/IY’
register pairs (including each register's Extended portion).
When doing context switching, by exceptional condition
(trap or interrupts) or by subroutine/procedure calls, the
CPU has to save the contents of the registers currently in
use, along with the current CPU status.
Traditionally in the Z80 CPU architecture, this is done by
saving the contents of the register into memory, usually
using push/pop instructions or the auxiliary register file.
Register contents are then restored when the process is
finished.
With the Z380 CPU’s multiple register banks, saving the
contents of the working register set currently in use is just
a matter of an instruction to change the field in the Select
Register, which allows fast context switching.
1.4 SUMMARY
The Z380 CPU is a high-performance 16-bit Central Pro-
cessing Unit Superintegration
™ core. Code-compatible
with the Z80 CPU, the Z380 CPU architecture has been
expanded to include features such as multiple register
banks, 4 Gbytes of linear memory addressing space, and
efficient handling of nested interrupts. The benefits of this
architecture, including high throughput rates, code den-
sity, and compiler efficiency, greatly enhance the power
and versatility of the Z380 CPU. Thus, the Z380 CPU
provides both a growth path for existing Z80-based de-
signs and a powerful processor for applications and the
products to be developed around this CPU core.
Zilog’s products are not authorized for use as critical compo-
nents in life support devices or systems unless a specific written
agreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
Telex 910-338-7621
FAX 408 370-8056
Internet: http://www.zilog.com
© 1994, 1995, 1996, 1997 by Zilog, Inc. All rights reserved. No
part of this document may be copied or reproduced in any form
or by any means without the prior written consent of Zilog, Inc.
The information in this document is subject to change without
notice. Devices sold by Zilog, Inc. are covered by warranty and
patent indemnification provisions appearing in Zilog, Inc. Terms
and Conditions of Sale only.
ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY,
IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMA-
TION SET FORTH HEREIN OR REGARDING THE FREEDOM OF
THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY
INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MER-
CHANTABILITY OR FITNESS FOR ANY PURPOSE.
Zilog, Inc. shall not be responsible for any errors that may appear
in this document. Zilog, Inc. makes no commitment to update or
keep current the information contained in this document.