Zilog Z80380 - Manual (Page 225)

U SER ' S M ANUAL Z ILOG
U SER ’s M ANUAL
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PPENDIX
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Z380 ™ CPU I NSTRUCTION F ORMATS
Four formats are used to generate the machine language
bit encoding for the Z380 CPU instructions. Also, the Z380
CPU has eight Decoder Directives which work as a special
escape sequence to the certain instructions, to expand its
capability as explained in Chapter 3.
The bit encoding of the Z380 CPU instructions are parti-
tioned into bytes. Every instructions encoding contains
one byte dedicated to specifying the type of operation to
be performed; this byte is referred to as the instruction’s
operation code, or opcode. Besides specifying a particu-
lar operation, opcode typically include bit encoding speci-
fying the operand addressing mode for the instruction and
identifying any general purpose registers used by the
instruction. Along with the opcode, instruction encoding
may include bytes that contain an address, displacement,
and/or immediate value used by the instruction, and spe-
cial bytes called “escape codes” that determine the mean-
ing of the opcode itself.
By themselves, one byte opcode would allow the encoding
of only 256 unique instructions. Therefore, special “es-
cape codes” that precede the opcode in the instruction
encoding are used to expand the number of possible
instructions. There are two types of escape codes; ad-
dressing mode and opcode. Escape codes for the Z80
original instructions are one bytes in length, and the
escape codes used to expand the Z380 instructions are
one or two bytes in length.
These instruction formats are differentiated by the opcode
escape value used. Format 1 is for instructions without an
opcode escape byte(s), Format 2 is for instructions with an
opcode escape byte. Format 3 is for instructions whose
opcode escape byte has the value 0CBH, and Format 4 is
for instructions whose escape bytes are 0ED, followed by
0CBH.
For the opcode escape byte, the Z380 CPU uses 0DDH
and 0FDH as well, which on the Z80 CPU, these are used
only as an address escape byte.
In Format 2 and 4, the opcode escape byte immediately
precedes the opcode byte itself.
In Format 3, a 1-byte displacement may be between the
opcode escape byte and opcode itself. Opcode escape
bytes are used to distinguish between two different in-
structions with the same opcode bytes, thereby allowing
more than 256 unique instructions. For example, the 01H
opcode, when alone, specifies a form of a Load Register
Word instruction; when proceeded by 0CBH escape code,
the opcode 01H specifies a Rotate Left Circular instruc-
tion.
Format 3 instructions with DDIR Immediate data Decoder
Directives, 1 to 3 bytes of displacement is between the
opcode escape byte and opcode itself.
Format 4 instructions are proceeded by 0EDH, 0CBH, and
a opcode. Optionally, with immediate word field follows.
Addressing mode escape codes are used to determine
the type of encoding for the addressing mode field within
an instruction’s opcode, and can be used in instructions
with and without opcode escape value. An addressing
mode escape byte can have the value of 0DDH or 0FDH.
The addressing mode escape byte, if present, is always
the first byte of the instruction’s machine code, and is
immediately followed by either the opcode (Format 1), or
the opcode escape byte (Format 2 and 3). For example,
the 46H opcode, when alone, specifies a Load B register
from memory location pointed by (HL) register; when
proceeded by the 0DDH escape byte, the opcode 46H
specifies a Load B register from the memory location
pointed by (IX+d).