Zilog Z80380 - Manual (Page 215)

6-1
Z380 ™
U SER ' S M ANUAL Z ILOG
DC-8297-03
6.1 INTRODUCTION
U SER ’s M ANUAL
C
HAPTER
6
I NTERRUPTS A ND T RAPS
Exceptions are conditions that can alter the normal flow of
program execution. The Z380
™ CPU supports three kinds
of exceptions; interrupts, traps, and resets.
Interrupts are asynchronous events generated by a device
external to the CPU; peripheral devices use interrupts to
request service from the CPU. Traps are synchronous
events generated internally in the CPU by a particular
condition that can occur during the attempted execution of
an instruction—in particular, when executing undefined
instructions. Thus, the difference between Traps and Inter-
rupts is their origin. A Trap condition is always reproduc-
ible by re-executing the program that created the Trap,
whereas an Interrupt is generally independent of the
currently executing task.
A hardware reset overrides all other conditions, including
Interrupts and Traps. It occurs when the /RESET line is
activated and causes certain CPU control registers to be
initialized. Resets are discussed in detail in Chapter 7.
The Z380 MPU’s Interrupt and Trap structure provides
compatibility with the existing Z80 and Z180 MPU’s with
the following exception—the undefined opcode Trap oc-
currence is with respect to the Z380 instruction set, and its
response is improved (vs the Z180) to make Trap handling
easier. The Z380 MPU also offers additional features to
enhance flexibility in system design.
6.2 INTERRUPTS
Of the five external Interrupt inputs provided, one is as-
signed as a Nonmaskable Interrupt, /NMI. The remaining
inputs, /INT3-/INT0, are four asynchronous maskable In-
terrupt requests.
The Nonmaskable Interrupt; (NMI) is an Interrupt that
cannot be disabled (masked) by software. Typically NMI is
reserved for high priority external events that need imme-
diate attention, such as an imminent power failure. Maskable
Interrupts are Interrupts that can be disabled (masked)
through software by cleaning the appropriate bits in the
Interrupt Enable Register (IER) and IEF1 bit in the Select
Register (SR).
All of these four maskable Interrupt inputs (/INT3-/INT0)
are external input signals to the Z380 CPU core. The four
Interrupt enable bits in the Interrupt Enable Register deter-
mine (IER; Internal I/O address: 17H) which of the re-
quested Interrupts are accepted. Each Interrupt input has
a fixed priority, with /INT0 as the highest and /INT3 as the
lowest.
The Enable Interrupt (EI) instruction is used to selectively
enable the maskable Interrupts (by setting the appropriate
bits in the IER register and IEF1 bit in the SR register) and
the Disable Interrupt instruction is used to selectively
disable interrupts (by clearing appropriate bits in the IER,
and/or clearing IEF1 bit in the SR register). When an
Interrupt source has been disabled, the CPU ignores any
request from that source. Because maskable Interrupt
requests are not retained by the CPU, the request signal on
a maskable Interrupt line must be asserted until the CPU
acknowledges the request.
When enabling Interrupts with the EI instruction, all
maskable Interrupts are automatically disabled (whether
previously enabled or not) for the duration of the execution
of the EI instruction and the instruction immediately follow-
ing.
Interrupts are always accepted between instructions. The
block move, block search, and block I/O instructions can
be interrupted after any iteration.
The Z380 CPU has four selectable modes for handling
externally generated Interrupts, using the IM instruction.
The first three modes extend the Z80 CPU Interrupt Modes
to accommodate the Z380 CPU’s additional Interrupt in-
puts in a compatible fashion. The fourth mode allows more
flexibility in interrupt handling.