Zilog Z80380 - Manual (Page 51)

5-17
Z380 ™
U SER ' S M ANUAL Z ILOG
DC-8297-03
5.5.12 Decoder Directives
The Decoder Directives (Table 5-17) are a special instruc-
tions to expand the Z80 instruction set to handle the Z380’s
4 Gbytes of linear memory addressing space. For details
on this instruction, refer to Chapter 3.
Table 5-17. Decoder Directive Instructions
DDIR W Word Mode
DDIR IB,W Immediate Byte, Word Mode
DDIR IW,W Immediate Word, Word Mode
DDIR IB Immediate Byte
DDIR LW Long Word Mode
DDIR IB,LW Immediate Byte, Long Word Mode
DDIR IW,LW Immediate Word, Long Word Mode
DDIR IW Immediate Word
5.6 NOTATION AND BINARY ENCODING
The rest of this chapter consists of a detailed description
of the Z380 CPU instructions, arranged in alphabetical
order by mnemonic. This section describes the notational
conventions used in the instruction descriptions and the
binary encoding for register fields within the instruction’s
operation codes (opcodes).
The description of each instruction begins on a new page.
The instruction mnemonic and name are printed in bold
letters at the top of each page to enable the reader to easily
locate a desired description. The assembly language
syntax is then given in a single generic form that covers all
the variants of the instruction, along with a list of applicable
addressing modes. This is followed by a description of the
operation performed by the instruction in “pseudo Pascal”
fashion, a detailed description, a listing of all the flags that
are affected by the instruction, and illustrations of the
opcodes for all variants of the instruction.
Symbols. The following symbols are used to describe the
instruction set.
n An 8-bit constant
nn A 16-bit constant
d An 8-bit offset. (two’s complement)
src Source of the instruction
dst Destination of the instruction
SR Select Register
R Any register. In Word operation, any register pair.
Any 8-bit register (A, B, C, D, E, H, or L) for Byte
operation.
IR Indirect register
RX Indexed register (IX or IY) in Word operation, IXH,
IXL, IYH, or IYL for Byte operation.
SP Current Stack Pointer
(C) I/O Port pointed by C register
cc Condition Code
[ ] Optional field
( ) Indirect Address Pointer or Direct Address
Assignment of a value is indicated by the symbol "
←
”. For
example,
dst
←
dst + src
indicates that the source data is added to the destination
data and the result is stored in the destination location.
The symbol “
↔
” indicates that the source and destination
is swapping. For example,
dst
↔
src
indicates that the source data is swapped with the data in
the destination; after the operation, data at “src” is in the
“dst” location, and data in “dst “ is in the “src” location.
The notation “dst (b)” is used to refer to bit “b” of a given
location, “dst(m-n)” is used to refer to bit location m to n of
the destination. For example,
HL(7) specifies bit 7 of the destination.
and
HL(23-16) specifies bit location 23 to 16 of the HL
register.
Flags. The F register contains the following flags followed
by symbols.
S Sign Flag
Z Zero Flag
H Half Carry Flag
P/V Parity/Overflow Flag
N Add/Subtract Flag
C Carry Flag