Zilog Z80380 - Manual (Page 55)

5-21
Z380 ™
U SER ' S M ANUAL Z ILOG
DC-8297-03
ADC
ADD WITH CARRY (WORD)
ADC HL,src dst = HL
src = BC, DE, HL, SP
Operation: HL(15-0)
←
HL(15-0) + src(15-0) + C
The source operand together with the Carry flag is added to the HL register and the sum is
stored in the HL register. The contents of the source are unaffected. Two’s complement
addition is performed.
Flags: S: Set if the result is negative; cleared otherwise
Z: Set if the result is zero; cleared otherwise
H: Set if there is a carry from bit 11 of the result; cleared otherwise
V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the
result is of the opposite sign; cleared otherwise
N: Cleared
C: Set if there is a carry from the most significant bit of the result; cleared otherwise
Addressing Execute
Mode Syntax Instruction Format Time Note
R: ADC HL,R 11101101 01rr1010 2
Field Encodings: rr: 00 for BC, 01 for DE, 10 for HL, 11 for SP