Zilog Z80380 - Manual (Page 16)

2-1
Z380 ™
U SER ' S M ANUAL Z ILOG
DC-8297-03
2.1 INTRODUCTION
U SER ’s M ANUAL
C
HAPTER
2
A DDRESS S PACES
The Z380 CPU supports five address spaces correspond-
ing to the different types of locations that can be ad-
dressed and the method by which the logical addresses
are formed. These five address spaces are:
■ CPU Register Space. This consists of all the register
addresses in the CPU register file.
■ CPU Control Register Space. This consists of the
Select Register (SR).
■ Memory Address Space. This consists of the
addresses of all locations in the main memory.
2.2 CPU REGISTER SPACE
The Z380 register file is illustrated in Figure 2-1. Note that
this figure shows the configuration of the register on the
Z380 CPU, and the number of the register files may vary on
future Superintegration devices. The Z380 CPU contains
abundant register resources. At any given time, the pro-
gram has immediate access to both primary and alternate
registers in the selected register set. Changing register
sets is a simple matter of an LDCTL instruction to program
the Select Register (SR).
The CPU register file is divided into five groups of registers
(an apostrophe indicates a register in the auxiliary regis-
ters).
■ Four sets of Flag and Accumulator registers (F, A, F’,
A’)
■ Four sets of Primary and Working registers (B, C, D, E,
H, L, B’, C’, D’, E’, H’, L’)
■ External I/O Address Space. This consists of all
external I/O ports addresses through which peripheral
devices are accessed.
■ On-Chip I/O Address Space. This consists of all
internal I/O port addresses through which peripheral
devices are accessed. Also, this addressing space
contains registers to control the functionality of the
device, giving status information.
■ Four sets of Index registers (IX, IY, IX’, IY’)
■ Stack Pointer (SP)
■ Program Counter, Interrupt register, Refresh register
(PC, I, R)
Register addresses are either specified explicitly in the
instruction or are implied by the semantics of the instruc-
tion.