Zilog Z80380 - Manual (Page 205)

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Z380 ™
U SER ' S M ANUAL Z ILOG
DC-8297-03
SRLW
SHIFT RIGHT LOGICAL (WORD)
SRLW dst dst = R, RX, IR, X
Operation: tmp
←
dst
C
←
dst(0)
dst(15)
←
0
dst(n)
←
tmp(n+1) for n = 0 to 14
The contents of the destination operand are shifted right one bit position. Bit 0 of the
destination operand is moved to the Carry flag and zero is shifted into the most significant
bit of the destination.
Flags: S: Cleared
Z: Set if the result is zero; cleared otherwise
H: Cleared
P: Set if parity of the result is even; cleared otherwise
N: Cleared
C: Set if the bit shifted from bit 0 was a 1; cleared otherwise
Addressing Execute
Mode Syntax Instruction Format Time Note
R: SRLW R 11101101 11001011 001110rr 2
RX: SRLW RX 11101101 11001011 0011110y 2
IR: SRLW (HL) 11101101 11001011 00111010 2+r
X: SRLW (XY+d) 11y11101 11001011 ——d— 00111010 4+r I
Field Encodings: rr: 00 for BC, 01 for DE, 11 for HL
y:
0 for IX, 1 for IY