Zilog Z80380 - Manual (Page 127)

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Z380 ™
U SER ' S M ANUAL Z ILOG
DC-8297-03
LDCTL
LOAD CONTROL REGISTER (BYTE)
LDCTL dst,src dst = DSR, XSR, YSR
src = A, IM
or
dst = A
src = DSR, XSR, YSR
or
dst = SR
src = A, IM
Operation: if (dst = SR) then begin
SR(31-24)
←
src
SR(23-16)
←
src
SR(15-8)
←
src
end
else begin
dst
←
src
end
The contents of the source are loaded into the destination.
Flags: S: Unaffected
Z: Unaffected
H: Unaffected
V: Unaffected
N: Unaffected
C: Unaffected
Load into Control Register
Addressing
Execute
Mode Syntax Instruction Format Time Note
R: LDCTL SR,A 11011101 11001000 4
LDCTL Rd,A 11qq1101 11011000 4
IM: LDCTL SR,n 11011101 11001010 ——n— 4
LDCTL Rd,n 11qq1101 11011010 ——n— 4
Field Encodings: qq: 01 for XSR, 10 for DSR, 11 for YSR
Load from Control Register
Addressing
Execute
Mode Syntax Instruction Format Time Note
R: LDCTL A,Rs 11qq1101 11010000 2
Field Encodings: qq: 01 for XSR, 10 for DSR, 11 for YSR