Zilog Z80380 User Manual

Page 219

6-5

Z380

™

SER

ANUAL

ILOG

DC-8297-03

6.4 NONMASKABLE INTERRUPT

The Nonmaskable Interrupt Input /NMI is edge sensitive,
with the Z380 MPU internally latching the occurrence of its
falling edge. When the latched version of /NMI is recog-
nized, the following operations are performed.

The Interrupted PC (Program Counter) value is pushed
onto the stack. The size of the PC value pushed onto
the stack depends on Native (one word) or Extended
mode (two words) in effect.

The state of IEF1 is copied to IEF2, then IEF1 is
cleared.

The Z380 MPU commences to fetch and execute
instructions from address 00000066H.

6.5 INTERRUPT RESPONSE FOR MASKABLE INTERRUPT ON /INT0

The transactions caused by the Maskable Interrupt on
/INT0 are different depends on the Interrupt Mode in effect
at the time when the interrupt has been accepted, as
described below.

6.5.1 Interrupt Mode 0 Response for
Maskable Interrupt /INT0

This mode is similar to the 8080 CPU Interrupt response
mode. During the Interrupt acknowledge transaction, the
external I/O device being acknowledged is expected to
output a vector onto the upper portion of the data bus, D15-
D8. The Z380 MPU interprets the vector as an instruction
opcode. IEF1 and IEF2 are reset to logic 0, disabling all
further maskable interrupt requests. Note that unlike the
other interrupt responses, the PC is not automatically
pushed onto the stack. Typically, a Restart instruction
(RST) is used, since the Restart opcode is only one byte
long, meaning that the interrupting peripheral needs to
supply only one byte of information. For this case, it pushes
the interrupted PC (Program Counter) value onto the stack
and resumes execution at a fixed memory location. Alter-
natively, a 3-byte call to any location can be executed.

Note that a Trap occurs if an undefined opcode is supplied
by the I/O device as a vector.

6.5.2 Interrupt Mode 1 Response for
Maskable Interrupt /INT0

In Interrupt Mode 1, the Z380 CPU automatically executes
a Restart to a fixed location (00000038H) when an interrupt
occurs. An Interrupt acknowledge transaction is gener-
ated, during which the data bus contents are ignored by
the Z380 MPU. The interrupted PC value is pushed onto the
stack. The size of the PC value pushed onto the stack is
depends on Native (one word) or Extended mode (two
words) in effect. The IEF1 and IEF2 are reset to logic 0 so
as to disable further maskable interrupt requests. Instruc-
tion fetching and execution restarts at memory location
00000038H.

6.5.3 Interrupt Mode 2 Response for
Maskable Interrupt /INT0

Interrupt Mode 2 is a vectored Interrupt response mode,
wherein the interrupting device identifies the starting loca-
tion of service routine using an 8-bit vector read by the CPU
during the Interrupt acknowledge cycle.

During the Interrupt acknowledge transaction, the external
I/O device being acknowledged is expected to output a
vector onto the upper portion of the data bus, D15-D8. The
interrupted PC value is pushed onto the stack and IEF1
and IEF2 are reset to logic 0 so as to disable further
maskable interrupt requests. The size of the PC value
pushed onto the stack is depends on Native (one word) or
Extended mode (two words) in effect. The Z380 MPU then
reads an entry from a table residing in memory and loads
it into the PC to resume execution. The address of the table
entry is composed of the I Extend (Iz) contents as A31-A16,
the I Register contents as A15-A8 and the vector supplied
by the I/O device as A7-A0. Note that the table entry is
effectively the starting address of the interrupt service
routine designed for the I/O device being acknowledged,
and the table composing of starting addresses for all the
Interrupt Mode 2 service routines can be referred to as the
Interrupt Mode 2 vector table. Each table entry should be
word-sized if the Z380 MPU is in the Native mode and Long
Word-sized if in the Extended mode, in either case even-
aligned (least significant byte with address A0 = 0), mean-
ing 128 different vectors can be used in the Native mode,
and 64 different vectors can be used in Extended mode.

6.5.4 Interrupt Mode 3 Response for
Maskable Interrupt /INT0

Interrupt Mode 3 is similar to mode 2 except that a 16-bit
vector is expected to be placed on the data bus D15-D0 by
the I/O device during the Interrupt acknowledge transac-
tion. The interrupted PC is pushed onto the stack. The size
of the PC value pushed onto the stack depends on the