Zilog Z80380 - Manual (Page 5)

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Z380 ™
U SER ' S M ANUAL Z ILOG
DC-8297-03
1.2 CPU ARCHITECTURE
The Z380 CPU is a binary-compatible extension of the Z80
CPU and the Z180 CPU architecture. High throughput
rates are achieved by a high clock rate, high bus band-
width, and instruction fetch/execute overlap. Communi-
cating to the external world through an 8-bit or 16-bit data
bus, the Z380 CPU is a full 32-bit machine internally, with
a 32-bit ALU and 32-bit registers.
1.2.1 Modes of Operation
To maintain compatibility with the Z80/Z180 CPU while
having the capability to manipulate 4 Gbytes of memory
address range, the Z380 CPU has two bits in the Select
Register (SR) to control the modes of operation. One bit
controls the address manipulation mode: Native mode or
Extended mode; and the other bit controls the data ma-
nipulation mode: Word mode or Long Word mode. In
result, the Z380 CPU has four modes of operation. On
reset, the Z380 CPU is in Native/Word mode, which is
compatible to the Z80/Z180’s operation mode. For details
on this subject, refer to Chapter 3, “Native/Extended Mode,
Word/Long Word Mode of Operation, and Decoder Direc-
tive Instructions.”
1.2.1.1 Native Mode and Extended Mode
The Z380 CPU can operate in either Native or Extended
mode, as controlled by a bit in the Select Register (SR). In
Native mode (the Reset configuration), all address ma-
nipulations are performed modulo 65536 (2
16 ). In this
mode, the Program Counter (PC) only increments across
16 bits, all address manipulation instructions (increment,
decrement, add, subtract, indexed, stack relative, and PC
relative) only operate on 16 bits, and the Stack Pointer (SP)
only increments and decrements across 16 bits. The PC
high-order word is left at all zeros, as the high-order words
of the SP and the I register. Thus, Native mode is fully
compatible with the Z80 CPU’s 64 Kbyte address mode. It
is still possible to address memory outside of 64 Kbyte
address space for data storage and retrieval in Native
mode, however, since direct addresses, indirect addresses,
and the high-order word of the SP, I, and the IX and IY
registers may be loaded with non-zero values. Executed
code and interrupt service routines must reside in the
lowest 64 Kbytes of the address space.
In Extended mode, however, all address manipulation
instructions operate on 32 bits, allowing access to the
entire 4 Gbyte address space of the Z380 CPU. In both
Native and Extended modes, the Z380 drives all 32 bits of
the address onto the external address bus; only the width
of the manipulated addresses distinguishes Native from
Extended mode. The Z380 CPU implements one instruc-
tion to allow switching from Native to Extended mode
(SETC XM); however, once in Extended mode, only Reset
will return the Z380 CPU to Native mode. This restriction
applies because of the possibility of “misplacing” interrupt
service routines or vector tables during the transition from
Extended mode back to Native mode.
1.2.1.2 Word or Long Word Mode
In addition to Native and Extended mode, which are
specific to memory space addressing, the Z380 CPU can
operate in either Word or Long Word mode specific to data
load and exchange operations. In Word mode (the Reset
configuration), all word load and exchange operations
manipulate 16-bit quantities. For example, only the low-
order words of the source and destination are exchanged
in an exchange operation, with the high-order words
unaffected.
In the Long Word mode, all 32 bits of the source and
destination are exchanged. The Z380 CPU implements
two instructions plus decoder directives to allow switching
between Word and Long Word mode; SETC LW (Set
Control Long Word) and RESC LW (Reset Control Long
Word) perform a global switch, while DDIR W, DDIR LW
and their variants are decoder directives that select a
particular mode only for the instruction that they precede.
Note that all word data arithmetic (as opposed to address
manipulation arithmetic), rotate, shift, and logical opera-
tions are always in 16-bit quantities. They are not con-
trolled by either the Native/Extended or Word/Long Word
selections. The exceptions to the 16-bit quantities are, of
course, those multiply and divide operations with 32-bit
products or dividends.
All word Input/Output operations are performed on 16-bit
values, regardless of Word/Long Word operation.
1.2.2 Address Spaces
Addressing spaces in the Z380 CPU include the CPU
register, the CPU control register, the memory address,
on-chip I/O address, and the external I/O address. The
CPU register space is a superset of the Z80 CPU register
set, and consists of all of the registers in the CPU register
file. These CPU registers are used for data and address
manipulation, and are an extension of the Z80 CPU register
set, with four sets of this extended Z80 CPU register set
present in the Z380 CPU. Access to these registers is
specified in the instruction, with the active register set
selected by bits in the Select Register (SR) in the CPU
control register space.