Zilog Z80380 - Manual (Page 18)

2-3
Z380 ™
U SER ' S M ANUAL Z ILOG
DC-8297-03
2.2.1 Primary and Working Registers
The working register set is divided into two register files:
the primary file and the alternate file (designated by prime
(‘)). Each file contains an 8-bit accumulator (A), a Flag
register (F), and six 8-bit general-purpose registers (B, C,
D, E, H, and L) with their Extended registers. Only one file
can be active at any given time, although data in the
inactive file can still be accessed by using EX R, R’
instructions for the byte-wide registers, EX RR, RR’ instruc-
tions for register pairs (either in 16-bit or 32-bit wide
depending on the LW status). Exchange instructions allow
the programmer to exchange the active file with the inac-
tive file. The EX AF, AF’, EXX, or EXALL instructions
changes the register files in use. Upon reset, the primary
register file in register set 0 is active. Changing register
sets is a simple matter of an LDCTL instruction to program
SR.
The accumulator is the destination register for 8-bit arith-
metic and logical operations. The six general-purpose
registers can be paired (BC, DE, and HL), and are ex-
tended to 32 bits by the extension to the register (with suffix
“z”; BCz/DEz/HLz), to form three 32-bit general-purpose
registers. The HL register serves as the 16-bit or 32-bit
accumulator for word operations. Access to the Extended
portion of the registers is possible using the SWAP instruc-
tion or word Load instructions in Long Word operation
mode.
The Flag register contains eight status flags. Four can be
individually used for control of program branching, two are
used to support decimal arithmetic, and two are reserved.
These flags are set or reset by various CPU operations. For
details on Flag operations, refer to Section 5.2, “Flag
Register.”
2.2.2. Index Registers
The four index registers, IX, IX’, IY, and IY’, are extended
to 32 bits by the extension to the register (with suffix “z”;
IXz/IYz), to form 32-bit index registers. To access the
Extended portion of the registers use the SWAP instruction
or word Load instructions in Long Word operation mode.
These Index registers hold a 32-bit base address that is
used in the Index addressing mode.
Only one register of each can be active at any given time,
although data in the inactive file can still be accessed by
using EX IX, IX’ and EX IY, IY’ (either in 16-bit or 32-bit wide
depending on the LW bit status). Index registers can also
function as general-purpose registers with the upper and
lower bytes of the lower 16 bits being accessed individu-
ally. These byte registers are called IXU, IXU’, IXL, and IXL’
for the IX and IX’ registers, and IYU, IYU’, IYL, and IYL’ for
the IY and IY’ registers.
Selection of primary or auxiliary Index registers can be
made by EXXX, EXXY, or EXALL instructions, or program-
ming of SR. Upon reset, the primary registers in register set
0 is active. Changing register sets is a simple matter of an
LDCTL instruction to program SR.
2.2.3. Interrupt Register
The Interrupt register (I) is used in interrupt modes 2 and
3 for /INT0 to generate a 32-bit indirect address to an
interrupt service routine. The I register supplies the upper
24 or 16 bits of the indirect address and the interrupting
peripheral supplies the lower eight or 16 bits. In Assigned
Vectors mode for /INT3-/INT1, the upper 16 bits of the
vector are supplied by the I register; bits 15-9 are supplied
from the Assigned Vector Base register, and bits 8-0 are
the assigned vector unique to each of /INT3-/INT1.
2.2.4. Program Counter
The Program Counter (PC) is used to sequence through
instructions in the currently executing program and to
generate relative addresses. The PC contains the 32-bit
address of the current instruction being fetched from
memory. In Native mode, the PC is effectively only 16 bits
long, since the upper word [PC31-PC16] of the PC is
forced to zero, and when carried from bit 15 to bit 16 (Lower
word [PC15-PC0] to Upper word [PC31-PC16]) are inhib-
ited in this mode. In Extended mode, the PC is allowed to
increment across all 32 bits.
2.2.5. R Register
The R register can be used as a general-purpose 8-bit
read/write register. The R register is not associated with
the refresh controller and its contents are changed only by
the user.
2.2.6. Stack Pointer
The Stack Pointer (SP) is used for saving information when
an interrupt or trap occurs and for supporting subroutine
calls and returns. Stack Pointer relative addressing allows
parameter passing using the SP. The SP is 16 bits wide, but
is extended by the SPz register to 32 bits wide.