Zilog Z80380 - Manual (Page 35)

5-1
Z380 ™
U SER ' S M ANUAL Z ILOG
DC-8297-03
5.1 INTRODUCTION
U SER ’s M ANUAL
C
HAPTER
5
I NSTRUCTION S ET
The Z380 ™ CPU instruction set is a superset of the Z80 CPU
and the Z180 MPU; the Z380 CPU is opcode compatible
with the Z80 CPU/Z180 MPU. Thus, a Z80/Z180 program
can be executed on a Z380 CPU without modification. The
instruction set is divided into 12 groups by function:
■ 8-Bit Load/Exchange Group
■ 16/32-Bit Load, Exchange, SWAP and Push/Pop Group
■ Block Transfers, and Search Group
■ 8-Bit Arithmetic and Logic Operations
■ 16/32-Bit Arithmetic Operations
■ 8-Bit Bit Manipulation, Rotate and Shift Group
■ 16-Bit Rotates and Shifts
5.2 PROCESSOR FLAGS
The Flag register contains six bits of status information that
are set or cleared by CPU operations (Figure 5-1). Four of
these bits are testable (C, P/V, Z, and S) for use with
conditional jump, call, or return instructions. Two flags are
not testable (H and N) and are used for binary-coded
decimal (BCD) arithmetic. The Flag register provides a link between sequentially
executed instructions, in that the result of executing one
instruction may alter the flags, and the resulting value of the
flags can be used to determine the operation of a subse-
quent instruction. The program control instructions, whose
operation depends on the state of the flags, are the Jump,
Jump Relative, subroutine Call, Call Relative, and subrou-
tine Return instructions; these instructions are referred to
as conditional instructions.
Figure 5-1. Flag Register
■ Program Control Group
■ Input and Output Operations for External I/O Space
■ Input and Output Operations for Internal I/O Space
■ CPU Control Group
■ Decoder Directives
This chapter describes the instruction set of the Z380 CPU.
Flags and condition codes are discussed in relation to the
instruction set. Then, the interpretability of instructions and
trap are discussed. The last part of this chapter is a
detailed description of each instruction, listed in alphabeti-
cal order by mnemonic. This section is intended as a
reference for Z380 CPU programmers. The entry for each
instruction contains a complete description of the instruc-
tion, including addressing modes, assembly language
mnemonics, and instruction opcode formats.
S Z X H X P/V N C
7 6 5 4 3 2 1 0