Zilog Z80380 - Manual (Page 212)

5-178
Z380 ™
U SER ' S M ANUAL
DC-8297-03
Z ILOG
TSTIO
TEST I/O PORT
TSTIO src src = IM
Operation: (C) AND src
A logical AND operation is performed between the corresponding bits of the source and the
contents of the I/O location. The contents of both the I/O location and the source are
unaffected; only the flags are modified as a result of this instruction. No external I/O
transaction will be generated as a result of this instruction, although the I/O address will
appear on the adress bus while the internal read is occurring. The peripheral address in the
C register is placed on the low byte of the address bus and zeros are placed on all other
address lines.
Flags: S: Set if the most significant bit of the result is set; cleared otherwise
Z: Set if all bits of the result are zero; cleared otherwise
H: Set
P: Set if the parity is even; cleared otherwise
N: Cleared
C: Cleared
Addressing Execute
Mode Syntax Instruction Format Time Note
TSTIO n 11101101 01110100 ——n— 3+i