Zilog Z80380 - Manual (Page 223)

U SER ' S M ANUAL Z ILOG
Table 7-1. Effect of a Reset on Z380 CPU and Related I/O Registers
Register Reset Value Comments
Program Counter 00000000 PCz, PC
Stack Pointer 00000000 SPz, SP
I 000000 Iz, I
R 00
Select Register 00000000 Register Bank 0 Selected:
AF, Main Bank, IX, IY
Native Mode
Maskable Interrupts Disabled, in Mode 0
Bus Request Lock-Off
A and F Registers Register Banks 3-0:
A, F, A’, F’ Unaffected
Register Extensions 0000 Register Bank 0:
BCz, DEz, HLz, IYz,
BCz’, DEz’, HLz’, IYz’
(All “non-extended” portions unaffected.)
Register Bank 3-1 Unaffected.
I/O Bus Control Register 0 00 IOCLK = BUSCLK/8
Interrupt Enable Register 01 /INT0 Enabled
Assigned Vector Base Register 00
Trap and Break Register 00