Altera Stratix V Avalon-ST User Manual
User guide
Table of contents
Document Outline
- Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the SR-IOV DMA Example Design
- Generating the Example Design Testbench
- Understanding the Generated Files and Directories
- Simulating the SR--IOV Example Design
- Running A Gate-Level Simulation
- Understanding the DMA Functionality
- Compiling the Example Design with the Quartus II Software
- Using the IP Catalog To Generate Your Stratix V Hard IP for PCI Express as a Separate Component
- 3. Parameter Settings
- 4. Interfaces and Signal Descriptions
- Avalon-ST TX Interface
- Avalon‑ST RX Interface
- BAR Hit Signals
- Configuration Status Interface
- Completion Side Band Signals
- Clock Signals
- Function-Level Reset Interface
- Interrupt Interface
- Implementing MSI-X Interrupts
- LMI Signals
- Reset, Status, and Link Training Signals
- Transceiver Reconfiguration
- Serial Data Signals
- Test Signals
- PIPE Interface Signals
- 5. Registers
- Correspondence between Configuration Space Registers and the PCIe Specification
- PCI and PCI Express Configuration Space Registers
- MSI Registers
- MSI-X Capability Structure
- Power Management Capability Structure
- PCI Express Capability Structure
- ARI Enhanced Capability Header and Control Register
- Advanced Error Reporting (AER) Enhanced Capability Header Register
- SR-IOV Virtualization Extended Capabilities Registers
- Advanced Error Capabilities and Control Register
- VF Base Address Registers (BARs) 0-5
- SR-IOV Enhanced Capability Registers
- InitialVFs and TotalVFs Registers
- VF Device ID Register
- Page Size Registers
- VF Base Address Registers (BARs) 0-5
- Secondary PCI Express Extended Capability Header
- Lane Error Status Register
- Uncorrectable Error Status Register
- Uncorrectable Error Mask Register
- Uncorrectable Error Severity Register
- Correctable Error Status Register
- Correctable Error Mask Register
- Virtual Function Registers
- 6. Reset and Clocks
- 7. Programming and Testing SR-IOV Bridge MSI Interrupts
- 8. Error Handling
- 9. IP Core Architecture
- 10. Design Implementation
- 11. Transceiver PHY IP Reconfiguration
- 12. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- B. Additional Information