Example designs, Debug features – Altera Stratix V Avalon-ST User Manual
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Example Designs
Altera provides example designs to familiarize you with the available functionality. Each design connects
the device under test (DUT) to an application programming platform (APP), labeled APPs in the figure
below. Certain critical parameters of the APPs component are set to match the values of the DUT. If you
change these parameters, you must change the APPs component to match. You can change the values for
all other parameters of the DUT without editing the APPs component.
In this example design, the following parameters must be set to match the values set in the DUT:
• Targeted Device Family
• Lanes
• Lane Rate
• Application Clock Rate
• Port type
• Application Interface
• Tags supported
• Maximum payload size
• Total PFs
• Total VFs
The following Qsys example designs are available for the Stratix V Hard IP for PCI Express with SR-IOV.
You can download them from the
directory:
• sriov_top_dma_gen2_x8_128b.qsys
• sriov_top_dma_gen2_x8_256b.qsys
• sriov_top_dma_gen3_x8_256b.qsys
• sriov_top_target_gen2_x8_256b_2pf.qsys
• sriov_top_target_gen3_x8_256b_1pf_32vf.qsys
• sriov_top_target_gen3_x8_256b_2pf_128vf.qsys
• sriov_top_target_gen3_x8_256b_2pf_4vf.qsys
• sriov_top_target_gen3_x8_256b_1pf_4vf_avmm.qsys
Related Information
Getting Started with the SR-IOV DMA Example Design
Debug Features
Debug features allow observation and control of the Hard IP for faster debugging of system-level
problems.
Related Information
UG-01097_sriov
2014.12.15
Example Designs
1-7
Datasheet
Altera Corporation