Altera Stratix V Avalon-ST User Manual
Page 61
Signal
Direction
Description
reset_status
Output
Active high reset status signal. When asserted, this signal
indicates that the Hard IP clock is in reset. The
reset_status
signal is synchronous to the
pld_clk
clock and is deasserted only
when the
npor
is deasserted and the Hard IP for PCI Express is
not in reset (
reset_status_hip
= 0). You should use
reset_
status
to drive the reset of your Application Layer. It resets the
Hard IP at power-up, for hot reset and link down events.
serdes_pll_locked
Output
When asserted, indicates that the PLL that generates the
coreclkout_hip
clock signal is locked. In pipe simulation mode
this signal is always asserted.
testin_zero
Output
When asserted, indicates accelerated initialization for simulation
is active.
Table 4-14: Status and Link Training Signals
The following table describes additional signals related to the reset function for the including the
ltsssm_state[4:0]
bus that indicates the current link training state. These signals are not top-level signals of the
Stratix V Hard IP for PCI Express IP Core with SR-IOV. They are listed here to assist in debugging link training
issues.
Signal
Direction
Description
cfg_par_err
Output
Indicates that a parity error in a TLP routed to the internal
Configuration Space. This error is also logged in the Vendor
Specific Extended Capability internal error register. You must
reset the Hard IP if this error occurs.
derr_cor_ext_rcv
Output
Indicates a corrected error in the RX buffer. This signal is for
debug only. It is not valid until the RX buffer is filled with data.
This is a pulse, not a level, signal. Internally, the pulse is
generated with the 500 MHz clock. A pulse extender extends the
signal so that the FPGA fabric running at 250 MHz can capture
it. Because the error was corrected by the IP core, no Application
Layer intervention is required.
derr_cor_ext_rpl
Output
Indicates a corrected ECC error in the retry buffer. This signal is
for debug only. Because the error was corrected by the IP core,
no Application Layer intervention is required.
derr_rpl
Output
Indicates an uncorrectable error in the retry buffer. This signal is
for debug only.
1
(4)
Debug signals are not rigorously verified and should only be used to observe behavior. Debug signals
should not be used to drive logic custom logic.
4-26
Reset, Status, and Link Training Signals
UG-01097_sriov
2014.12.15
Altera Corporation
Interfaces and Signal Descriptions