Altera Stratix V Avalon-ST - Manual (Page 17)

Understanding the DMA Functionality
The following figures illustrate the DMA functionality using numbered steps.
Figure 2-3: Steps to Fetch Descriptor Table from Host Memory
Rd_DC0 Rd_DC1 Rd_DC2 Rd_DC3
Read DMA Router
APPs - sriov_dma_app_g3x8_256b.qsys
rddc_ctl - rddc_ctl_256b.qsys wrdc_ctl - wrdc_ctl_256b.qsys
Wr_DC0 Wr_DC1 Wr_DC2 Wr_DC3
Write DMA Router
DMA Write TX Slave RX Master DMA Read
1
3
2
4
Stratix V Hard IP for PCI Express
SR-IOV Bridge
User Application Logic (On-Chip Memories)
sriov_top_dma_gen3_x8_256.qsys
Fetching the Descriptor Table entries includes the following steps:
1. The host sets up descriptor controller register table using the RX master interface.
2. The Descriptor Controller instructs the DMA Read module to fetch the descriptor instruction entries.
3. The Host returns descriptor instruction entries to the Descriptor Controller.
4. In response to the Descriptor Controller instruction, the DMA Read drives a Memory Read Request to
the Hard IP.
2-6 Understanding the DMA Functionality
UG-01097_sriov
2014.12.15
Altera Corporation Getting Started with the SR-IOV DMA Example Design
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