Features – Altera Stratix V Avalon-ST User Manual
Page 3
Table 1-1: PCI Express Data Throughput
The following table shows the aggregate bandwidth of a PCI Express link for Gen1, Gen2, and Gen3 for supported
link widths. The protocol specifies 2.5 giga-transfers per second for Gen1, 5.0 giga-transfers per second for Gen2,
and 8.0 giga-transfers per second for Gen3. This table provides bandwidths for a single transmit (TX) or receive
(RX) channel. The numbers double for duplex operation. Gen1 and Gen2 use 8B/10B encoding which introduces
a 20% overhead. In contrast, Gen3 uses 128b/130b encoding which reduces the data throughput lost to encoding
to less than 1%.
Link Width
×2
×4
×8
PCI Express Gen1 (2.5 Gbps) - 128-bit interface
N/A
N/A
16
PCI Express Gen2 (5.0 Gbps) - 128-bit interface
N/A
16
32
PCI Express Gen2 (5.0 Gbps) - 256-bit interface
N/A
N/A
32
PCI Express Gen3 (8.0 Gbps) - 128-bit interface
15.75
31.51
N/A
PCI Express Gen3 (8.0 Gbps) - 256-bit interface
N/A
N/A
63
Related Information
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Features
New features in the Quartus
®
II 14.1 software release:
• Reduced Quartus II compilation warnings by 50%.
The Stratix V Hard IP for PCI Express with SR-IOV supports the following features:
• Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as
hard IP.
• Support for ×2, ×4, and ×8 configurations with Gen1, Gen2, or Gen3 lane rates for Endpoints.
Downtrains to appropriate configuration when plugged into a lower bandwidth configuration,
including Gen1 x1, Gen1 x2, and so on.
• Dedicated 16 KByte receive buffer.
• Optional hard reset controller for Gen2.
• Qsys example designs demonstrating parameterization, design modules, and connectivity.
• Extended credit allocation settings to better optimize the RX buffer space based on application type.
• End-to-end cyclic redundancy code (ECRC) generation and checking and advanced error reporting
(AER) for high reliability applications.
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Features
UG-01097_sriov
2014.12.15
Altera Corporation
Datasheet