Altera Stratix V Avalon-ST Instruction Manuals and User Guides
We have 3 Instruction Manuals and User Guides for Stratix V Avalon-ST Altera
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 158 |
| Size: | 1.58 MB |
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Document Outline
- Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the SR-IOV DMA Example Design
- Generating the Example Design Testbench
- Understanding the Generated Files and Directories
- Simulating the SR--IOV Example Design
- Running A Gate-Level Simulation
- Understanding the DMA Functionality
- Compiling the Example Design with the Quartus II Software
- Using the IP Catalog To Generate Your Stratix V Hard IP for PCI Express as a Separate Component
- 3. Parameter Settings
- 4. Interfaces and Signal Descriptions
- Avalon-ST TX Interface
- Avalon‑ST RX Interface
- BAR Hit Signals
- Configuration Status Interface
- Completion Side Band Signals
- Clock Signals
- Function-Level Reset Interface
- Interrupt Interface
- Implementing MSI-X Interrupts
- LMI Signals
- Reset, Status, and Link Training Signals
- Transceiver Reconfiguration
- Serial Data Signals
- Test Signals
- PIPE Interface Signals
- 5. Registers
- Correspondence between Configuration Space Registers and the PCIe Specification
- PCI and PCI Express Configuration Space Registers
- MSI Registers
- MSI-X Capability Structure
- Power Management Capability Structure
- PCI Express Capability Structure
- ARI Enhanced Capability Header and Control Register
- Advanced Error Reporting (AER) Enhanced Capability Header Register
- SR-IOV Virtualization Extended Capabilities Registers
- Advanced Error Capabilities and Control Register
- VF Base Address Registers (BARs) 0-5
- SR-IOV Enhanced Capability Registers
- InitialVFs and TotalVFs Registers
- VF Device ID Register
- Page Size Registers
- VF Base Address Registers (BARs) 0-5
- Secondary PCI Express Extended Capability Header
- Lane Error Status Register
- Uncorrectable Error Status Register
- Uncorrectable Error Mask Register
- Uncorrectable Error Severity Register
- Correctable Error Status Register
- Correctable Error Mask Register
- Virtual Function Registers
- 6. Reset and Clocks
- 7. Programming and Testing SR-IOV Bridge MSI Interrupts
- 8. Error Handling
- 9. IP Core Architecture
- 10. Design Implementation
- 11. Transceiver PHY IP Reconfiguration
- 12. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- B. Additional Information
| Recognized languages: | English |
|---|---|
| Pages: | 293 |
| Size: | 2.34 MB |
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Document Outline
- Stratix V Avalon-ST Interface for PCIe Solutions User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Stratix V Hard IP for PCI Express
- Qsys Design Flow
- Generating the Testbench
- Simulating the Example Design
- Generating Quartus II Synthesis Files
- Understanding the Files Generated
- Understanding Simulation Log File Generation
- Understanding Physical Placement of the PCIe IP Core
- Compiling the Design in the Qsys Design Flow
- Modifying the Example Design
- Using the IP Catalog To Generate Your Stratix V Hard IP for PCI Express as a Separate Component
- Qsys Design Flow
- 3. Getting Started with the Configuration Space Bypass Mode Qsys Example Design
- 4. Parameter Settings
- 5. Interfaces and Signal Descriptions
- Avalon‑ST RX Interface
- Avalon‑ST RX Component Specific Signals
- Data Alignment and Timing for the 64‑Bit Avalon‑ST RX Interface
- Data Alignment and Timing for the 128‑Bit Avalon‑ST RX Interface
- Data Alignment and Timing for 256‑Bit Avalon‑ST RX Interface
- Tradeoffs to Consider when Enabling Multiple Packets per Cycle
- Avalon-ST TX Interface
- Clock Signals
- Reset, Status, and Link Training Signals
- ECRC Forwarding
- Error Signals
- Interrupts for Endpoints
- Interrupts for Root Ports
- Completion Side Band Signals
- Configuration Space Bypass Mode Interface Signals
- Parity Signals
- LMI Signals
- Transaction Layer Configuration Space Signals
- Hard IP Reconfiguration Interface
- Power Management Signals
- Physical Layer Interface Signals
- Avalon‑ST RX Interface
- 6. Registers
- Correspondence between Configuration Space Registers and the PCIe Specification
- Type 0 Configuration Space Registers
- Type 1 Configuration Space Registers
- PCI Express Capability Structures
- Altera-Defined VSEC Registers
- CvP Registers
- Uncorrectable Internal Error Mask Register
- Uncorrectable Internal Error Status Register
- Correctable Internal Error Mask Register
- Correctable Internal Error Status Register
- 7. Reset and Clocks
- 8. Interrupts
- 9. Error Handling
- 10. IP Core Architecture
- 11. Transaction Layer Protocol (TLP) Details
- 12. Throughput Optimization
- 13. Design Implementation
- 14. Optional Features
- 15. Hard IP Reconfiguration
- 16. Transceiver PHY IP Reconfiguration
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- DMA Write Cycles
- DMA Read Cycles
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- ebfm_barwr Procedure
- ebfm_barwr_imm Procedure
- ebfm_barrd_wait Procedure
- ebfm_barrd_nowt Procedure
- ebfm_cfgwr_imm_wait Procedure
- ebfm_cfgwr_imm_nowt Procedure
- ebfm_cfgrd_wait Procedure
- ebfm_cfgrd_nowt Procedure
- BFM Configuration Procedures
- BFM Shared Memory Access Procedures
- BFM Log and Message Procedures
- Verilog HDL Formatting Functions
- Procedures and Functions Specific to the Chaining DMA Design Example
- Debugging Simulations
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- B. Lane Initialization and Reversal
- C. Additional Information
| Recognized languages: | English |
|---|---|
| Pages: | 286 |
| Size: | 2.31 MB |
Show table of contents
Document Outline
- Arria V GZ Avalon-ST Interface for PCIe Solutions User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Arria V GZ Hard IP for PCI Express
- Qsys Design Flow
- Generating the Testbench
- Simulating the Example Design
- Generating Quartus II Synthesis Files
- Understanding the Files Generated
- Understanding Simulation Log File Generation
- Understanding Physical Placement of the PCIe IP Core
- Compiling the Design in the Qsys Design Flow
- Modifying the Example Design
- Using the IP Catalog To Generate Your Arria V GZ Hard IP for PCI Express as a Separate Component
- Qsys Design Flow
- 3. Getting Started with the Configuration Space Bypass Mode Qsys Example Design
- 4. Parameter Settings
- 5. Interfaces and Signal Descriptions
- Avalon‑ST RX Interface
- Avalon‑ST RX Component Specific Signals
- Data Alignment and Timing for the 64‑Bit Avalon‑ST RX Interface
- Data Alignment and Timing for the 128‑Bit Avalon‑ST RX Interface
- Data Alignment and Timing for 256‑Bit Avalon‑ST RX Interface
- Tradeoffs to Consider when Enabling Multiple Packets per Cycle
- Avalon-ST TX Interface
- Clock Signals
- Reset, Status, and Link Training Signals
- ECRC Forwarding
- Error Signals
- Interrupts for Endpoints
- Interrupts for Root Ports
- Completion Side Band Signals
- Parity Signals
- LMI Signals
- Transaction Layer Configuration Space Signals
- Hard IP Reconfiguration Interface
- Power Management Signals
- Physical Layer Interface Signals
- Avalon‑ST RX Interface
- 6. Registers
- Correspondence between Configuration Space Registers and the PCIe Specification
- Type 0 Configuration Space Registers
- Type 1 Configuration Space Registers
- PCI Express Capability Structures
- Altera-Defined VSEC Registers
- CvP Registers
- Uncorrectable Internal Error Mask Register
- Uncorrectable Internal Error Status Register
- Correctable Internal Error Mask Register
- Correctable Internal Error Status Register
- 7. Reset and Clocks
- 8. Interrupts
- 9. Error Handling
- 10. IP Core Architecture
- 11. Transaction Layer Protocol (TLP) Details
- 12. Throughput Optimization
- 13. Design Implementation
- 14. Optional Features
- 15. Hard IP Reconfiguration
- 16. Transceiver PHY IP Reconfiguration
- 17. Testbench and Design Example
- Endpoint Testbench
- Root Port Testbench
- Chaining DMA Design Examples
- Test Driver Module
- DMA Write Cycles
- DMA Read Cycles
- Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- ebfm_barwr Procedure
- ebfm_barwr_imm Procedure
- ebfm_barrd_wait Procedure
- ebfm_barrd_nowt Procedure
- ebfm_cfgwr_imm_wait Procedure
- ebfm_cfgwr_imm_nowt Procedure
- ebfm_cfgrd_wait Procedure
- ebfm_cfgrd_nowt Procedure
- BFM Configuration Procedures
- BFM Shared Memory Access Procedures
- BFM Log and Message Procedures
- Verilog HDL Formatting Functions
- Procedures and Functions Specific to the Chaining DMA Design Example
- Debugging Simulations
- 18. Debugging
- A. Transaction Layer Packet (TLP) Header Formats
- B. Lane Initialization and Reversal
- C. Additional Information