Altera Stratix V Avalon-ST User Manual
Page 38
Signal
Direction
Description
tx_st_valid
(3)
Input
Clocks
tx_st_data
to the core when
tx_st_ready
is also
asserted. Between
tx_st_sop
and
tx_st_eop
,
tx_st_valid
must
not be deasserted in the middle of a TLP except in response to
tx_st_ready
deassertion. When
tx_st_ready
deasserts, this
signal must deassert within 1 or 2 clock cycles. When
tx_st_
ready
reasserts, and
tx_st_data
is in mid-TLP, this signal must
reassert within 2 cycles. The figure entitled 64-Bit Transaction
Layer Backpressures the Application Layer illustrates the timing of
this signal.
To facilitate timing closure, Altera recommends that you register
both the
tx_st_ready
and
tx_st_valid
signals. If no other
delays are added to the ready-valid latency, the resulting delay
corresponds to a
readyLatency
of 2.
tx_st_empty[1:0]
Input
Indicates the number of qwords that are empty during cycles that
contain the end of a packet. When asserted, the empty dwords
are in the high-order bits. Valid only when
tx_st_eop
is asserted.
Not used when
tx_st_data
is 64 bits. For 128-bit data, only bit 0
applies and indicates whether the upper qword contains data. For
256-bit data, both bits are used to indicate the number of upper
words that contain data, resulting in the following encodings for
the 128-and 256-bit interfaces:
128-Bit interface:
tx_st_empty
= 0,
tx_st_data[127:0]
contains
valid data
tx_st_empty
= 1,
tx_st_data[63:0]
contains valid
data.
256-bit interface:
tx_st_empty
= 0,
tx_st_data[255:0]
contains
valid data
tx_
st_empty
= 1,
tx_st_data[191:0]
contains valid
data
tx_st_empty
= 2,
tx_st_data[127:0]
contains valid data
tx_st_empty
= 3,
tx_st_data[63:0]
contains valid data.
tx_st_err
Input
Indicates an error on transmitted TLP. This signal is used to
nullify a packet. It should only be applied to posted and
completion TLPs with payload. To nullify a packet, assert this
signal for 1 cycle after the SOP and before the EOP. When a
packet is nullified, the following packet should not be transmitted
until the next clock cycle.
tx_st_err
is not available for packets
that are 1 or 2 cycles long.
Refer to the figure entitled 128-Bit Avalon-ST tx_st_data Cycle
Definition for 3-Dword Header TLP with non-Qword Aligned
Address for a timing diagram that illustrates the use of the error
signal. Note that it must be asserted while the valid signal is
asserted.
UG-01097_sriov
2014.12.15
Avalon-ST TX Interface
4-3
Interfaces and Signal Descriptions
Altera Corporation