Altera Stratix V Avalon-ST User Manual
Page 104
Address
(hex)
Name
Description
0x084
PCI Express Device Capabil‐
ities Register
PCI Express Device Capabilities Register. The VF Device
Capabilities Register supports the same fields as the PF Device
Capabilities Register.
0x088
PCI Express Device Control
and Status Registers
The lower 16 bits implement the PCI Express Device Control
Register. The upper 16 bits implement the Device Status Register.
Refer to
for descriptions of the implemented fields.
0x08C
Link Capabilities Register
A read to any VF with this address returns the Link Capabilities
Register settings of the parent PF.
0x090
Link Control and Status
Registers
This register is not implemented for VFs, and reads as all 0s.
0x0A4 Device Capabilities 2
Registers
A read to any VF with this address returns the Device Capabili‐
ties 2 Register settings of the parent PF.
0x0A8 Device Control 2 and Status
2 Registers
This register is not implemented for VFs. A read to this address
returns all 0s.
0x0AC Link Capabilities 2 Register This register is not implemented for VFs. A read to this address
returns all 0s.
0x0B0
Link Control 2 and Status 2
Registers
This register contains control and status bits for the PCIe link.
For VFs, bit[16] stores the current de-emphasis level setting for
the parent PF. All other bits are reserved.
Alternate RID (ARI) Capability Structure
0x100
ARI Enhanced Capability
Header
PCI Express Extended Capability ID for ARI and Next Capability
pointer. The Next Capability pointer points to NULL.
0x104
ARI Capability Register, ARI
Control Register
This register is not implemented for VFs. A read to this address
returns all 0s.
Table 5-47: Command and Status Register for VFs
Bits
Register Description
Default Value
Access
Command Register
[1:0]
Reserved.
0
RO
[2]
Bus Master enable. When set, the VF can generate transactions as
a bus master.
0
RW
[15:3]
Reserved.
0
RO
Status Register
5-30
Virtual Function Registers
UG-01097_sriov
2014.12.15
Altera Corporation
Registers