Device identification registers – Altera Stratix V Avalon-ST User Manual
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Parameter
Value
Description
Prefetch‐
able
Prefetchable
Non-Prefetchable
Defining memory as prefetchable allows data in the
region to be fetched ahead anticipating that the
requestor may require more data from the same
region than was originally requested. If you specify
that a memory is prefetchable, it must have the
following 2 attributes:
• Reads do not have side effects
• Write merging is allowed
Size
16 Bytes–2 GBytes
Specifies the memory size.
Device Identification Registers
Table 3-3: Device ID Registers
The following table lists the default values of the read-only Device ID registers. You can use the parameter editor
to change the values of these registers. At run time, you can change the values of these registers using the optional
reconfiguration block signals. You can specify Device ID registers for each Physical Function.
Register Name
Range
Default Value
Description
Vendor ID
16 bits
0x00000000
Sets the read-only value of the
Vendor ID
register. This
parameter can not be set to 0xFFFF per the PCI Express
Specification.
Address offset: 0x000.
Device ID
16 bits
0x00000000
Sets the read-only value of the
Device ID
register.
Address offset: 0x000.
Revision ID
8 bits
0x00000000
Sets the read-only value of the
Revision ID
register.
Address offset: 0x008.
Class code
24 bits
0x00000000
Sets the read-only value of the
Class Code
register.
Address offset: 0x008.
Subsystem
Vendor ID
16 bits
0x00000000
Sets the read-only value of the
Subsystem Vendor ID
register in the PCI Type 0 Configuration Space. This
parameter cannot be set to 0xFFFF per the PCI Express
Base Specification. This value is assigned by PCI-SIG to
the device manufacturer.
Address offset: 0x02C.
3-6
Device Identification Registers
UG-01097_sriov
2014.12.15
Altera Corporation
Parameter Settings