Altera Stratix V Avalon-ST - Manual (Page 69)

Figure 4-16: Arria V GZ and Stratix V GX/GT/GS Gen1 and Gen2 Channel Placement Using the ATX PLL
Selecting the ATX PLL has the following advantages over selecting the CMU PLL:
• The ATX PLL saves one channel in Gen1 and Gen2 ×1, ×2, and ×4 configurations.
• The ATX PLL has better jitter performance than the CMU PLL.
Note: You must use the soft reset controller when you select the ATX PLL and you cannot use CvP.
ATX PLL0
Ch5
Ch3
Ch2
Ch1
Ch0
ATX PLL0
Ch4
PCIe Hard IP
ATX PLL1
Ch0
Ch5
Ch3
Ch2
Ch1
Ch0 ATX PLL0
Ch4 ATX PLL1
PCIe Hard IP
Ch0
Ch1
Ch5
Ch3
Ch2
Ch1
Ch0
ATX PLL0
ATX PLL0
Ch4
PCIe Hard IP
ATX PLL1
Ch0
Ch1
Ch2
Ch3
Ch5
Ch3
Ch2
Ch1
Ch0
ATX PLL0
ATX PLL1 Ch4
ATX PLL1
Ch0
Ch1
Ch2
Ch3
Ch11
Ch9
Ch8
Ch7
Ch6
Ch10
PCIe Hard IP
Ch5
Ch6
Ch7
Ch4
x1
x8
x2
x4
4-34 Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
UG-01097_sriov
2014.12.15
Altera Corporation Interfaces and Signal Descriptions
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