Altera Stratix V Avalon-ST - Manual (Page 55)

Signal Direction Description
app_int_pend_
status[1:0]
Input The Application Layer must drive each of these inputs with the
interrupt pending status of the corresponding PF. The Interrupt
Pending Status bit of the PCI Status Register records the pending
status .
app_int_sts_fn
Input Identifies the function generating the legacy interrupt. When
app_int_sts_fn
= 0, specifies status for PF0. When
app_int_
sts_fn
= 1, specifies status for PF1.
app_intx_disable[1:0]
Output This output is driven by the
INTDisable
bit of the PCI
Command Register of FP0 and PF1.
app_intx_disable[0]
disables PF0.
app_intx_disable[1]
disables PF1.
Figure 4-4: Legacy Interrupt Assertion
clk
app_int_sts_
app_int_ack
Figure 4-5: Legacy Interrupt Deassertion
clk
app_int_sts_
app_int_ack
Related Information
• Programming and Testing SR-IOV Bridge MSI Interrupts on page 7-1
• PCI Local Bus Specification, Revision 3.0
Implementing MSI-X Interrupts
Section 6.8.2 of the PCI Local Bus Specification describes the MSI-X capability and table structures. The
MSI-X capability structure points to the MSI-X Table structure and MSI-X Pending Bit Array (PBA)
registers. The BIOS sets up the starting address offsets and BAR associated with the pointer to the starting
address of the MSI-X table and PBA registers.
The following figure shows the Application Layer modules that implement MSI-X interrupts.
4-20 Implementing MSI-X Interrupts
UG-01097_sriov
2014.12.15
Altera Corporation Interfaces and Signal Descriptions
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