Altera Stratix V Avalon-ST User Manual
Page 134

Function Number Assignments
Function Type
6
Virtual Function 5 (optional)
7
Virtual Function 6 (optional)
Table 9-3: Function Address Map: Two PFs and No ARI
Function Number Assignments
Function Type
0
Physical Function 0
1
Physical Function 1
2
Virtual Function 0 (required)
3
Virtual Function 1 (required)
4
Virtual Function 2 (required)
5
Virtual Function 3 (required)
6
Virtual Function 4 (optional)
7
Virtual Function 5 (optional)
Table 9-4: Function Address Map: One PF and ARI
Function Number Assignments
Function Type
0
Physical Function 0
1–127
Reserved
128
Virtual Function 0 (required)
129
Virtual Function 1 (required)
130
Virtual Function 2 (required)
131
Virtual Function 3 (required)
132-255
Virtual Function 4-127 (optional)
9-10
Physical and Virtual Function Address Assignments
UG-01097_sriov
2014.12.15
Altera Corporation
IP Core Architecture
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)