Interrupt capabilities – Altera Stratix V Avalon-ST User Manual
Page 27
Register Name
Range
Default Value
Description
Subsystem
Device ID
16 bits
0x00000000
Sets the read-only value of the
Subsystem Device ID
register in the PCI Type 0 Configuration Space.
Address offset: 0x02C
Related Information
Interrupt Capabilities
Table 3-4: MSI anad MSI-X Interrupt Settings
Each Physical Function defines its own MSI-X table settings. The VF MSI-X table settings are the same for all the
Virtual Functions associated with each Physical Function.
Parameter
Value
Description
MSI Interrupt Settings
PF0 MSI Requests
1,2,4,8,16,32
Specifies the maximum number of MSI messages the Application
Layer can request. This value is reflected in Multiple Message
Capable field of the
Message Control
register, 0x050[31:16]. . For
MSI Interrupt Settings, if the PF MSI option is enabled, all PFs
support MSI capability.
PF1 MSI Requests
1,2,4,8,16,32
MSI-X Interrupt Settings
PF MSI-X
On/Off
When On, enables the MSI-X functionality. For PF and VF
MSI-X Interrupt Settings, if PF MSI-X is enabled, all PFs
supports MSI-X capability.
VF MSI-X
On/Off
Bit Range
MSI-X Table size
[10:0]
System software reads this field to determine the MSI-X Table
size
value of 2047 indicates a table size of 2048. This field is read-
only. Legal range is 0–2047 (2
11
).
Address offset: 0x068[26:16]
MSI-X Table
Offset
[31:0]
Specifies the offset from the BAR indicated in theMSI-X Table
BAR Indicator. The lower 3 bits of the table BAR indicator
(BIR) are set to zero by software to form a 32-bit qword-
aligned offset
(1)
. This field is read-only.
UG-01097_sriov
2014.12.15
Interrupt Capabilities
3-7
Parameter Settings
Altera Corporation