Altera Stratix V Avalon-ST - Manual (Page 80)

MSI Registers
Figure 5-2: MSI Register Byte Address Offsets and Layout
0x050
0x054
0x058
Message Control
Configuration MSI Control Status
Register Field Descriptions
Next Cap Ptr
Message Address
Message Upper Address
Reserved Message Data
31 24 23 16 15 8 7 0
0x05C
Capability ID
Table 5-4: MSI Control Register - 0x050
Bits Register Description Default Value Access
[31:25] Not implemented 0 RO
[24] Per-Vector Masking Capable. This bit is hardwired to 1. The
design always supports per-vector masking of MSI interrupts.
1
RO
[23] 64-bit Addressing Capable. When set, the device is capable of
using 64-bit addresses for MSI interrupts.
Set in Qsys RO
[22:20] Multiple Message Enable. This field defines the number of
interrupt vectors for this function. The following encodings are
defined:
• 3'b000: 1 vector
• 3'b001: 2 vectors
• 3'b010: 4 vectors
• 3'b011: 8 vectors
• 3'b100: 16 vectors
• 3'b101: 32 vectors
The
Multiple Message Capable
field specifies the maximum
value allowed.
0 RW
[19:17] Multiple Message Capable. Defines the maximum number of
interrupt vectors the function is capable of supporting. The
following encodings are defined:
• 3'b000: 1 vector
• 3'b001: 2 vectors
• 3'b010: 4 vectors
• 3'b011: 8 vectors
• 3'b100: 16 vectors
• 3'b101: 32 vectors
Set in Qsys RO
5-6 MSI Registers
UG-01097_sriov
2014.12.15
Altera Corporation Registers
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