Altera Stratix V Avalon-ST - Manual (Page 15)

6. Specify the following parameters:
Table 2-1: Parameters to Specify on the Generation Menu in Qsys
Parameter Value
Testbench System
Create testbench Qsys system Standard, BFMs for standard Avalon interfaces
Create testbench simulation model Verilog. This option generates simulation files for
the testbench.
Allow mixed-language simulation Leave this option off.
Output Directory
Path working_dir/
Testbench working_dir/testbench/
7. Click Generate.
Qsys generates the testbench.
8. To generate files for Quartus II compilation, on the Generate menu, select Generate HDL.
The Generation dialog box appears.
9. Specify the following parameters:
Table 2-2: Parameters to Specify on the Generation Menu in Qsys
Parameter Value
Verilog
Create HDL design files for synthesis Verilog.
Create timing and resource estimates for third-
party EDA synthesis tools
Leave this option off.
Create block symbol file (.bsf) Leave this option on.
Simulation
Create simulation model.
None . (You created the simulation model when
you generated the testbench.)
Allow mixed language simulation.
Leave this option off.
Output Directory
2-4 Generating the Example Design Testbench
UG-01097_sriov
2014.12.15
Altera Corporation Getting Started with the SR-IOV DMA Example Design
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