Uncorrectable error status register – Altera Stratix V Avalon-ST User Manual
Page 99
Bits
Register Description
Default Value
Accress
[31]
Reserved
0
RO
Uncorrectable Error Status Register
This register controls which errors are forwarded as internal uncorrectable errors. All of the errors are
severe and may place the device or PCIe link in an inconsistent state.
Table 5-41: Uncorrectable Error Status Register - 0x144 (ARI supported) or (0x104 ARI not supported)
Bits
Register Description
Default Value
Access
[31:21]
Reserved.
0
RO
[20]
When set, indicates an Unsupported Request Received
0
RW1C
[19]
When set, indicates an ECRC Error Detected
0
RW1C
[18]
When set, indicates a Malformed TLP Received
0
RW1C
[17]
When set, indicates Receiver Overflow
0
RW1C
[16]
When set, indicates an unexpected Completion was received
0
RW1C
[15]
When set, indicates a Completer Abort (CA) was transmitted
0
RW1C
[14]
When set, indicates a Completion Timeout
0
RW1C
[13]
When set, indicates a Flow Control protocol error
0
RW1C
[12]
When set, indicates that a poisoned TLP was received
0
RW1C
[11:5]
Reserved
0
RO
[4]
When set, indicates a Data Link Protocol error
0
RW1C
[3:0]
Reserved
0
RO
Related Information
UG-01097_sriov
2014.12.15
Uncorrectable Error Status Register
5-25
Registers
Altera Corporation