Altera Stratix V Avalon-ST User Manual
Page 76
Byte Address
SR-IOV Bridge Configuration Space Register
Corresponding Section in PCIe Specification
0x140:0x168 -
ARI supported
0x100:0x128 -
No ARI
support
Advanced Error Reporting AER (optional)
Advanced Error Reporting Capability
0x180:0x1BC
Single-Root I/O Virtualization (SR-IOV)
Capability Structure
(6)
SR-IOV Extended Capability Header in
Single Root I/O Virtualization and
Sharing Specification, Rev. 1.1
0x200:0x218
Secondary PCI Express Extended Capability
Structure
(7)
Secondary PCI Express Extended
Capability
0x21C:0xFFF
Reserved
N/A
Related Information
(6)
SR-IOV Capability only exists if you enable SR-IOV support
(7)
When you enable Gen3, the PF0 configuration space supports the Secondary PCI Express Extended
Capability Structure
5-2
Correspondence between Configuration Space Registers and the PCIe Specification
UG-01097_sriov
2014.12.15
Altera Corporation
Registers
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)